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Photonics: Deep Dive at DesignCon 2019

Photonics: Deep Dive at DesignCon 2019
Included will be emerging modulation schemes, complex 3D optical packaging, high channel losses, nonlinear optics, and thermal and low power requirements to enable high-performance and high-data-rate designs.

(Image source: Kelvinsong - Own work, CC0,

Integrating photonics or wireless technology into electrical designs presents unique technical and design challenges—whether at the chip, board, or system level. Track 3 at DesignCon 2019, January 29-31 in Santa Clara, CA, deals with the issues associated with emerging modulation schemes, complex 3D optical packaging, high channel losses, nonlinear optics, and thermal and low power requirements to enable high performance and high data rate designs.

This year, DesignCon will feature six sessions focused on photonics. As a co-chair of Track 3, I personally curated these sessions along with my co-chair, Jose Moreira. I am pleased to provide insight into the new research and information that will be presented.

See all of the photonics sessions at DesignCon 2019!

The availability of process design kits (PDKs) is the most fundamental building block to transition photonics technology from a few select research labs to a much more widely acceptable commercial product design flow. PDKs provide access to the foundry technology through the use of photonic-focused tools, such as simulation, schematic capture, and layout. In 2018, the first commercial PDKs that were delivered consisted of a few active and passive components. They linked photonic design tools to the commercial foundries, providing photonic designers an avenue to create commercially viable products.

The panel session, “Photonics Coming of Age: The Emergence of PDKs,” will focus on the challenges faced by the industry in developing silicon photonics PDKs, their usefulness in the product design, and how photonics PDK development will emerge in the future. The panel will discuss how EDA platforms are linked to the emerging commercial foundries, photonic PDKs, and verification flow to match the foundry process, assuring that designs created with these tools will meet the design specifications and are successfully fabricated at the foundry.

A three hour tutorial, “Lowering the Barrier to Entry for Electronic/Photonic ICs,” will demonstrate the industry's first commercially available silicon photonic IC design flow. The tutorial will showcase an electronic-photonic co-design and verification flow. Participants will have the opportunity to learn about the generation and use of parametrized photonic PDKs, compact model libraries (CMLs) for photonic components, and large-scale, mixed electronic-photonic design and simulation. The tutorial will also illustrate the latest advancements in DFM and yield analysis for EPICs and set the direction for future work in this field.

Specifications for the components used in optical communications systems are designed from the perspective of predicting how well a transmitter, channel, and receiver will interoperate at a system level. For NRZ systems, the key metrics for an optical transmitter included modulation power, extinction ratio, the eye-mask, and the transmitter dispersion penalty (TDP). TDP was the best predictor of interoperability, but was expensive and time consuming. The eye-mask was a loose predictor of interoperability. Because it was easy to measure and intuitively easy to understand, however, it became the primary metric for manufacturing test. Whenever there was a jump in data rates, it was very simple to scale the specifications to the new data rate. With 50 and 100 Gb/s links, simple scaling was not an option—either at the hardware or test level. New modulation schemes, like PAM4 test methods, were required, such as TDECQ measurements. The paper, “TDECQ for PAM4 Optical Transmitters: Does it Really Work?,” will provide insight into this new test methodology and the scenarios for which it can predict performance accurately—or not.

If you are required to use the TDECQ methodology, this session will provide you with a basic understanding and insight into what is going on 'underneath the hood' and what is required to achieve a reliable and useful metric.

The new 5G and WiGig standards present new challenges for the test and measurement of integrated circuits. The main challenges are the very high frequencies (e.g., as high as 44 GHz for 5G and 72 GHz for WiGig) and also the large number of ports, due to the use of phased-array antennas. Because these integrated circuits are intended for the consumer market, cost of test is a critical factor. The technical session, “A Review of Combiner/Divider PCB Design Topologies For 5G& WiGig ATE Applications,” will address the challenges of designing PCB test fixtures for automated test equipment (ATE) for millimeter wave applications intended for consumer applications like 5G and WiGig.

The need for higher bandwidth and data speed keeps increasing, driven by cloud/data center rapid build and expansion, and fueled by emerging data demanding AI (artificial intelligence), deep learning, and accelerating technologies. Meanwhile, the performance, power, and cost requirements—merited by bit error ratio (BER), latency, pJ/b, and $/Gbps—become more stringent at the next speed generation.

At 112 Gbps, it is getting increasingly difficult to improve the channel material for chip-to-chip (C2C) and chip-to optical module (C2M) for lower insertion loss (IL)—even when cost constraint is not considered, resulting in transceivers/SERDES with more capable and complex equalizations (e.g., CTLE+FFE and/or DFE) to meet the BER performance. This drives up latency, pJ/b, and $/Gbps figure of merits (FOMs). A new and novel approach/architecture is needed to solve those challenges versus conventional ones with board mounted and more complex transceivers/SERDES. A promising path is to shrink the conventional C2C and C2M interfaces from board mounted to within package. Consequently, the C2C and C2M interface becomes D2D (die-to-die) and D2OE (die-to-optical engine), giving rise to the desired latency, power, density, and cost FOMs.

The technical panel, “Ultra Short Reach (XSR) Electrical I/O Interfaces at 112G: Why, Challenges & Solutions,” will discuss XSR, its challenges, and the solutions for ultra-short reach (XSR) electrical I/O interfaces at 112G and beyond. The session will cover the benefits of such an interface along with plausible solutions and associated challenges.

While fully integrated smart sensors and devices are getting smaller and cheaper, communicating their data becomes the biggest cost factor. Conventional links like USB, WLAN, Bluetooth, ZigBee, and others are too expensive when selling price shall drop below $5.

Lastly, discussing a solution implemented for a medication transport temperature-tracking device of a Swiss company, the paper, “Lowest-cost Communication with light from an IoT Device to Smartphone,” will demonstrate the unidirectional data transfer of 84 Bytes of data from the LTI device (Long Term Indicator) to almost any smartphone in less than 10 seconds at almost no additional cost and using only 3 LEDs.

See all of the photonics sessions at DesignCon 2019!

Sanjeev Gupta is currently a product architect at Intel and co-chair of DesignCon’s Track 3 covering integrating photonics or wireless technology into electrical designs.

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