Reincarnated Return of the HRRG 4-Bit Computer (Part 3)

In Part 1 of this mega-mini-series, I introduced Joe Farr and we revisited the concept of the Heath Robinson Rube Goldberg (HRRG) 4-bit computer, which has been on the drawing board for longer than I care to remember. In Part 2, I introduced Nils van den Heuvel and we discussed how the registers in the HRRG’s CPU have evolved over the years (you may wish to bounce over to Part 2 and refresh your mind regarding these registers before proceeding further).

The next thing for us to consider is the HRRG’s instruction set, which has also seen more than a few changes since it was first conceived deep in the mists of time.

The HRRG’s Latest and Greatest Instruction Set

The first thing to remember is that we wanted to be able to use a single 4-bit nybble to specify which instruction we were talking about. Obviously, this limited us to only 16 instructions. There’s a lot to wrap one’s brain around here, and I don’t intend to go into too much detail, but there are a couple of points that are well worth noting.

First, we decided to implement an ADDC (“add with carry”) instruction rather than an ADD (“add without carry”) because these are necessary to implement multi-nybble operations, and it’s a lot easier to make an ADDC work like an ADD by setting the carry flag to 0 before performing the operation than it is to make an ADD work like an ADDC. Similarly, we opted for a SUBB (“subtract with borrow”) rather than a SUB (“subtract without borrow”) because it’s easier to make a SUBB work like a SUB by setting the carry flag to 1 before performing the operation than it is to make an SUB work like a SUBB.

The same thing applies to the ROLC (“rotate left through carry”) and RORC (“rotate right through carry”). It’s easier to use these as starting points to implement alternative rotate and shift operations than it is to go the other way round.

As we see in the illustration below, the instruction opcode is followed by additional nybble operands that are used to specify the (source of data), if any, and   (the target or destination of the result), if any. These may be accompanied by additional and operands if required (“aop” stands for “additional operand”).

Originally, we had opted for a approach, but once Nils commenced his FPGA implementation, he said that presenting things in the order would make his life easier, so that’s what we did.

One thing that’s worth emphasizing is that both the source and target can be a CPU register or a memory location. For example, we can add a nybble in a CPU register to a nybble in memory and store the result in the register or in the memory depending on which we define as the source and which we define as the target.

What’s Your Status?

Before we proceed, we really need to consider the HRRG’s status register, which is where we find the status bits (or flags) that reflect the results from an operation. In the case of the HRRG, we have two 4-bit status registers in the CPU that we call S0 and S1.

Since the HRRG has only 16 instructions, we don’t have any special instructions dedicated to clearing (to 0) or setting (to 1) the status bits. However, we can achieve the same effect using AND and OR operations. For example, if we wanted to clear the C flag, we could do so using the following instruction: 

AND %1011, S0

The corresponding machine code would be as follows:

$7 $A $B $4

Where $7 specifies the AND operation, $A says the source (the ) is a CV4 (constant 4-bit value), $B is the constant value itself (the ), and $4 says that the target (the ) is register S0 (since the target is a CPU register, there is no ).

As a somewhat related point, we don’t have special instructions to enable or disable interrupts. However, we can achieve the same effect by setting or clearing bit 0 in status register S1.

Most processors have an unconditional JMP (“jump”) instruction along with a suite of jumps based on the state of the status flags, like JZ (“jump if zero”), JNZ (“jump if not zero”), JN (“jump if negative”), JNN (“jump if not negative”), and so forth. We do things a little bit differently because we only have a JMP instruction. However, as discussed in point #10, this instruction is followed by a control nybble, which is used to perform both unconditional and conditional jumps. Also, even though we have only a JMP instruction at the CPU level, we can have JMP, JZ, HNZ, JN, JNN... etc. mnemonics in our assembly language because our assembler can translate these into the appropriate control codes.

Also of interest is the fact that our JSR (“jump to subroutine”) instruction has the same capabilities with regard to jumping depending on the values of status bits as does our JMP instruction.

And, as one more related point, we don’t have special “return from subroutine” or “return from interrupt” instructions. In this case, the same effect is achieved by popping the return address off the top of the stack into the PC.

When Instructions and Status Bits Collide

The following table illustrates which of the O (Overflow), C (Carry), Z (Zero) and N (Negative) status bits are affected by the various instructions. 

A Matrix of Possibilities

Given the fact that we have a 4-bit data bus, a 12-bit memory space, and both 4-bit and 12-bit CPU registers, things can become a tad confusing when transferring data back and forth between the 4-bit and 12-bit domains.

In the early days, Joe and I tried to tie the various possibilities down and capture our thoughts in the form of notes, but we were never 100% sure that we’d covered every conceivable combination and corner case. You can only imagine our chagrin when Nils came onboard and whipped up the following handy-dandy source-to-target data width mappings graphic.

As soon as I saw this chart, I thought (a) “That’s brilliant” and (b) “Why on Earth didn’t I think of that myself?”

So, that’s the current state of play. You are now up to date with where we are at with respect to the HRRG 4-bit computer. Nils is working away furiously on his gate/register-level FPGA-based implementation, about which I will blog further in the future. In the meantime, as always, I welcome your comments, questions, and suggestions.