DN Staff

February 4, 2002

3 Min Read
Chip makers seek speedy electrons

Moore's Law dictates that the number of transistors on microprocessors will double every 18 to 24 months. And indeed, the industry has kept up that blistering pace for nearly 30 years now.

But the dimensions of cutting-edge chips are approaching the atomic level; there's just no more room to shrink before electrons will leak between the ultra-thin wires. And a new chip-fabricating factory can cost $3-5 billion; a staggering investment that is tough to amortize over sales in a market where product lifetimes are shrinking.

Now there is a cheaper way to continue the march toward smaller, faster chips postulated by Moore, says Mark Wolf, president and CEO of AmberWave Systems, an MIT spinoff based here.

It's called strained silicon, and can create denser chips without changing the factory equipment.

In recent years, chip companies have continued to disaggregate, farming out R&D to their partners and suppliers. AmberWave hopes to fit into this equation by licensing intellectual property (IP) to those companies that are seeking better ways to build faster chips. And with five patents issued and 70 pending since their 1998 founding, they're making some headway.

But they're not alone-IBM has announced that it plans to sell strained silicon chips by 2003. "Most of the industry is struggling with extending chip performance as we approach the fundamental limits of silicon," said Randy Isaac, VP of science and technology for IBM research, in the company's June 8 announcement.

Isaac describes the process as aligning atoms within compounds so that the silicon is stretched (or "strained"), allowing electrons to flow with much less resistance, and up to 70% greater speed. That could allow chips to run 35% faster without shrinking their transistors.

Yet AmberWave claims it has a jump start on its giant competitor, since co-founder Gene Fitzgerald discovered the method in 1991. "We've been doing it so long, we know how to fix the problems," Wolf says. "People didn't believe us until IBM said it, too. But we believe they will eventually be a customer of ours."

Declaring that the future is in CMOS (complementary metal oxide semiconductor), AmberWave has patented its technique of "epsilon MOS": building chips from a layer of silicon over a silicon germanium (SiGe) buffer layer, on top of a silicon substrate. This "strained silicon" method can reduce power consumption or boost speed, while holding tools and equipment constant.

"We believe the ones going up today will be the last fabs that are built, because they're good enough," says Wolf. To encourage swift deployment of the new technology, AmberWave plans to keep royalty rates low, basing royalties on retail sales ("if it doesn't make them a better product, they don't owe us anything"), and avoiding exclusive licenses.

"We outsource everything but the technologists and their tools," Wolf says. "We don't touch the silicon infrastructure; we just put the magic on the wafer."

For more information about chips from AmberWave: Enter 534

Chips from IBM: Enter 535

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