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Want to Hail Engineering Excellence? Vote for the 2021 Engineer of the Year

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Cast your vote for the 2021 DesignCon Engineer of the Year. Let us know which of our four finalists you think should be the winner before noon PT on June 30, 2021.

The time has come for the engineering community to cast your vote for the DesignCon 2020 Engineer of the Year. This award is given out each year during the DesignCon event and seeks to recognize the best of the best in engineering and new product advancements at the chip, board, or system level, with a special emphasis on signal integrity and power integrity.

Editors of Design News and the staff of DesignCon would like to offer hearty congratulations to the finalists. For this year’s award, the winner (or his/her representative) will be able to direct a $1,000 donation to any secondary educational institution in the United States. The details on each nominee are below as provided in their published biographies and by the person/s who made the nomination. Please cast your vote by following this link.

Voting closes at noon Pacific Time on Wednesday, June 30. The winner will be announced at DesignCon 2021, August 16-18, 2021, at the San Jose McEnery Convention Center, San Jose, CA.

The four finalists for the 2021 DesignCon Engineer of the Year Award are (click each name to see finalist’s bio and community activity):

Cast your vote for the 2021 Engineer of the Year by noon PT, June 30.
See the Official Rules of the Engineer of the Year Award.
Learn more about DesignCon and register to attend.

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Cathy Liu

Distinguished Engineer & Director, Broadcom

Dr. Cathy Ye Liu, distinguished engineer and director, currently heads up Broadcom SerDes architecture and modeling group. Previously she worked as R&D director and distinguished engineer in Avago/LSI which acquired Broadcom. Since 2002, she has been working on high-speed transceiver solutions. Prior to this, she developed read channel and mobile digital TV receiver solutions. Her technical interests are signal processing, FEC, and modeling in high-speed optical and electrical transceiver solutions. She has published many journal and conference papers and holds 20+ US patents.

Cathy is an active member of the DesignCon Technical Program Committee and has been a long-time co-chair for Track 09 “Measurement, Simulation & Optimization of Jitter, Noise & Timing to Minimize Errors.” Cathy has also been a member on the DesignCon Panel; "Case of the Closing Eye" for over 9 years in a row. She is very connected to the DesignCon community as an active presenter on many topics related to chip design.

This year at DesignCon, Cathy will be presenting her paper at the technical session, “Salz SNR & Shannon Limit Study for the Next Speed Node Beyond 112Gbps (& up to 224Gbps),” the tutorial “What is FEC & How Do I Use It?,” and on the panel “The Case of the Closing Eyes: Testing for 400G.”

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Casey Morrison

VP of Products, Astera Labs

Casey Morrison is an accomplished system engineer with a record of developing innovative products and system level improvements to advance the industry. He actively engages with customers, industry peers, and technologists to enable seamless adoption of next-generation technologies in hardware designs. Casey has been involved in work to guide the industry through the changes and progression from 10-Gbps Ethernet to 800-Gbps Ethernet and 8-Gbps PCI Express (PCIe) to 32-Gbps Compute Express Link (CXL).

Casey first presented at DesignCon in 2013 when he collaborated with early adopters of 25-Gbps Ethernet. Since then, he has authored multiple white papers on 50G/100G PAM-4 technologies that discuss practical aspects of Signal Integrity including AC coupling capacitors, end-to-end system simulations, EMI issues and real-life considerations of Link Training just to name a few. Casey is actively involved in facilitating the transition of evolving Ethernet standards into high volume products.

As with Ethernet, Casey is a leading authority on PCI Express and Compute Express Link. At DesignCon 2020, Casey presented a step-by-step “how-to” guide for defining, executing, and analyzing system level simulations for PCIe 5.0 Root Complex, Retimer and End point. Casey is actively working with the industry to deploy CXL 2.0 solutions at scale.

Casey has received various industry recognitions during his career and is a recipient of the Raj Gupta System/Marketing Excellence award for being the top-performing engineer when he worked at Texas Instruments.

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Michael Schnecker

Business Development Manager, Rohde & Schwarz

Michael Schnecker’s experience in the test and measurement industry includes applications, sales and product development and specialization in signal integrity applications using oscilloscopes and other instruments. Prior to joining Rohde & Schwarz, Mike held positions at LeCroy and Tektronix. While at LeCroy, he was responsible for the deployment of the SDA series of serial data analyzers.     Mike has more than two decades of experience working with oscilloscope measurements. His background in time and frequency domains provides him with unique insight into the challenges engineers face when testing high-speed systems for both power and signal integrity. Interacting with engineers in the industry daily has allowed Mike to master the ability to explain complex measurement science to engineers at any level. He also holds several patents, including methods and apparatus for analyzing serial data streams as well as coherent interleaved sampling. Thus, Mike is recognized as a thought leader and exceptional mentor in the signal and power integrity community.

Mike has a BS from Lehigh University and an MS from Georgia Tech, both in electrical engineering. His experience in the test and measurement industry includes applications, sales and product development and he has specialized in signal integrity applications using oscilloscopes and other instruments. Prior to joining Rohde & Schwarz, Mike held positions at LeCroy and Tektronix. While at LeCroy, he was responsible for the deployment of the SDA series of serial data analyzers.

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Yuriy Shlepnev

President and Founder, Simberian

Yuriy Shlepnev is President and Founder of Simberian Inc., where he develops Simbeor electromagnetic signal integrity software. He received M.S. degree in radio engineering from Novosibirsk State Technical University in 1983, and the Ph.D. degree in computational electromagnetics from Siberian State University of Telecommunications and Informatics. He was principal developer of electromagnetic simulator for Eagleware Corporation and leading developer of electromagnetic software for simulation of signal and power distribution networks at Mentor Graphics. The results of his research are published in multiple papers and conference proceedings.

Yuriy conceived and brought to market a state of the art electromagnetic field solver tool suite and is considered an expert in his field and regularly posts teaching videos. He is a senior member of IEEE AP, MYY, EMC, and CPMT societies. He is also a Fellow of Kong’s Electromagnetics Academy and a member of the Applied Computational Electromagnetics Society (ACES).

Yuriy has been actively involved in the Technical Program Committee for DesignCon for many years and has served as track co-chair in the past.

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