Design Considerations for Maximizing Backplane Data Speeds

Global data consumption has been increasing rapidly and is expected to grow exponentially in the coming years. As the traditional Internet and the Internet of Things evolve and grow, the need for high-speed, high-density connectors grows with them. For example, new, flexible backplane solutions are needed to meet speed demands. Currently, users are demanding data rates from 25 Gbps to 40 Gbps, and 56 Gbps is on the horizon.

Not all backplanes are made alike, and they offer varied capabilities. System designers/architects that create networking, data center, storage, and other devices and systems need to understand key features -- such as required density, data-rate, slot pitch, and bandwidth -- that are used in individual chassis designs.

The most common design, a conventional backplane, uses a right-angle daughter card (RA DC) mated to vertical backplane headers. While this architecture is familiar to designers, compared to newer alternatives it requires longer routed channels and thicker substrates to meet signal density requirements and routing capabilities.

Longer routed channels have some benefits but also liabilities. They attenuate crosstalk (noise from adjacent channels) but cause greater insertion loss of the signals. The thicker substrates associated with conventional backplanes also present technical and commercial problems.

Thicker substrates require appropriate aspect ratios to control drill-hole locations with precision. Depending on the total substrate thickness and manufacturing process capabilities, a larger compliant pin may also be required to facilitate PCB fabrication. A larger compliant pin and its associated via diameter can cause a larger capacitive effect in the via structure, which can increase reflective loss in the channel. Back drilling (removing unused or unwanted PCB via stubs) may also be required to improve signal-integrity performance in the respective channel, and back drilling adds cost to PCB fabrication.

Backplane alternatives
All of these issues limit the ability of conventional backplanes to accommodate higher data speeds. As a result system designers are using several innovative solutions to resolve that issue, including the following.

The quad-route backplane is one solution. Some quad-route backplane connector solutions provide more column-to-column space than conventional designs. They enable the user to route four traces between the columns of vias by leveraging a 3-mm column-to-column pitch vs. the traditional, denser 1.9-mm pitch. This reduces the number of signal layers required to route the connector. Quad-route backplane solutions with 3-mm pitch provide lower crosstalk with a footprint that can produce robust signal-integrity performance. However, the increased pitch, which produces more spacing between wafers, means that fewer wafers can fit on a given card edge, reducing the connector linear density.

Another alternative, the coplanar backplane (right-angle male mating to right-angle daughtercard) supports various I/O protocols, enabling the use of pluggable modules. A coplanar backplane is essentially a bridge card; it provides a common interconnect for various blades, or line cards, that plug into the backplane. For example, some users may need to plug RJ45 blades into the backplane but other users, such as high-end data centers, may need faster data rates requiring a zQSFP type of I/O. On a coplanar backplane the user can change an Ethernet RJ45 connection to a SFP connection without unplugging anything from the backplane. This allows system designers to use existing backplane architectures while scaling to various I/O protocols, such as InfiniBand, Fibre Channel, and Ethernet.