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Vote for the 2018 DesignCon Engineer of the Year

DesignCon Engineer of the Year Award logo
It’s time to cast your vote for the 2018 DesignCon Engineer of the Year. Check out our six finalists and cast your vote by noon ET on Friday, January 12.

It’s time to cast your vote for the 2018 DesignCon Engineer of the Year. This award is given out each year during DesignCon and seeks to recognize the best of the best in engineering and new product advancements at the chip, board, or system level, with a special emphasis on signal integrity and power integrity.

The editors of Design News and the staff of DesignCon would like to offer hearty congratulations to the nominees. For this year’s award, the winner (or his/her representative) will be able to direct a $10,000 donation to any secondary educational institution in the United States. The details on each nominee are below as provided in their published biographies and by the person/s who made the nomination. Cast your vote here.

Voting closes at noon Eastern Time on Friday, January 12, 2018. The winner will be announced at DesignCon 2018, January 30-February 1, at the Santa Clara Convention Center, Santa Clara, CA.

The six finalists for the 2018 DesignCon Engineer of the Year Award are (click each name to see finalist’s bio and community activity):

Mike Peng Li

Fellow, Intel

Dr. Mike Peng Li is a Fellow at the Programmable Solution Group (formerly Altera Corp.), Intel Corporation. He is a corporate expert and adviser on jitter, noise, signal integrity, high-speed link, SERDES and on-die instrumentation (ODI), electrical and optical signaling, silicon photonics, and optical FPGA. Dr. Li was the Chief Technology Officer (CTO) for Wavecrest Corporation from 2000-2007, where he led the technology roadmap, leadership, vision, and product developments.

Mike has been a strong advocate for test & measurement, and signal integrity topics in the DesignCon community for more than 15 years. He has worked on many technical papers and panel topics related to the subject area of jitter & noise on serial data signaling. Mike has demonstrated leadership in the industry on developing interest and understanding around jitter topics for nearly 2 decades.

Mike has served on the DesignCon Technical Program Committee for over 15 years and leads conference planning as a co-chairperson for Track 9,  covering measurement, simulation, and optimization of jitter, noise, and timing to minimize errors. He is a standing member of the "Case of the Closing Eye" panel held annually at DesignCon and is an IEEE Fellow and chair/editor/member of OIF, IEEE 802.3 (Ethernet), PCI-SIG, and HMC standard committees.

This year at DesignCon, he is presenting at the tutorial, “Design & Verification for High-Speed I/Os at 10 to 112 Gbps With Jitter, Signal Integrity, and Power Optimization,” the panel, "The Case of the Closing Eyes: Is PAM the Answer?" and presenting in the technical sessions “Behavioral FEC Models for High Speed Serial Link BER Simulation,” “Effective Link Equalizations using FIR, CTLE, FFE, DFE, and FEC for Serial Links at 112 Gbps and Beyond,” and “Signaling and Performance Challenges and Solutions for Next-Generation OIF CEI-112G-VSR "Chip-to-Module" Interfaces.”

Cast your vote for the 2018 Engineer of the Year by noon ET, January 12.

Jose Moreira

Senior Staff Engineer, Advantest

Jose Moreira is a senior staff engineer in the test cell innovations team of the SOC business unit at Advantest in Böblingen, Germany. Mr. Moreira current work is on the challenges of IC characterization and testing, especially test fixture design for high-speed digital, mmwave (5G) and silicon photonics. He joined Agilent Technologies in 2001 (later Verigy and in 2011 acquired by Advantest) and holds a Master of Science degree in Electrical and Computer Engineering from the Instituto Superior Técnico, Lisbon University, Portugal. He is a senior member of the IEEE and co-author of the book An Engineer's Guide to Automated Testing of High-Speed Digital Interfaces.

Jose has been a driving force behind IEEE P370 which advances the technology behind de-embedded S-parameter measurements. He leads by example and routinely provides simulations, measurements and presentations of very high quality and conveys the material in an easy to follow format.

This year, Jose will be participating in the DesignCon panel, “Working Toward 5G: What's New From Previous Generations,” and presenting in the technical session, “A NIST Traceable PCB Kit for Evaluating the Accuracy of De-Embedding Algorithms and Corresponding Metrics.” Jose is an active member of the Technical Program Committee and serves as a co-chairperson on Track 3, photonic and electronic signaling, and has been a member of IEEE P370 for the past 2 years.

Cast your vote for the 2018 Engineer of the Year by noon ET, January 12.

Istvan Novak

Senior Principal Engineer, Oracle

Istvan Novak is a Senior Principle Engineer at Oracle. Besides signal integrity design of high-speed serial and parallel buses, he is engaged in the design and characterization of power-distribution networks and packages for mid-range servers. He creates simulation models, and develops measurement techniques for power distribution. Istvan has 20 plus years of experience with high-speed digital, RF, and analog circuit and system design. He is a Fellow of IEEE for his contributions to signal-integrity and RF measurement and simulation methodologies.

Istvan’s many years of significant contribution toward the advancing of signal and power integrity knowledge and practices have earned him a reputation of respect and admiration among his peers. His contribution to power and signal integrity analysis and measurements has made it possible identify and eliminate problems before they happen. His work through suppliers and academia has influenced and driven a change in the ways design, analysis, and measurement is done throughout the industry. 

Istvan has been presenting and teaching engineers at DesignCon for many years. He is considered an industry expert on power integrity and his papers continue to get reviewed and referenced year after year. He is easily approachable, happy to help young engineers. This year, Istvan will be participating in Tuesday’s keynote panel, “SI/PI & EMI Challenges: Looking Ahead Through 2023,” and the panel discussion, “Temperature and Bias Dependent Passive Component Models.” He will also be presenting in technical sessions, “How Spatial Variation of Voltage Regulator Output Impedance Depends on Sense Point and Bypass Capacitor Locations,” “Measuring Current and Current Sharing of DC-DC Converters,” and “Tale of a Differential Pair Measurement.” Istvan is an active member of the DesignCon Technical Program Committee, sharing his expertise by participating in the review of content for multiple tracks.

Istvan is an IEEE Fellow and has been a tutor at the University of Oxford, Oxford, UK for the past 10 years. He has also been a faculty member at CEI Europe AB since 1991 and served as Vice Dean of Faculty, Associate Professor at the Technical University of Budapest.

Cast your vote for the 2018 Engineer of the Year by noon ET, January 12.

Vishram Pandit

Platform Architect, Signal/Power Integrity, Intel

Vishram Pandit has been working in Power Integrity, Signal Integrity and EMC field for more than 20 years of which ~14 years were at Intel. He has been a key contributor to methodologies in on-chip power integrity, system level power integrity impact and signal/power integrity co-design, and successfully deploying those on various Intel products. Vishram led the Power Delivery & Integrity for memory technology at Intel California from 2004 to 2008. He established SoC and DRAM device PDN solution space and chip, package and PCB Power Integrity requirements and was Global Power Delivery Lead at SoC Development Group from 2008 to 2011. As a part of the IP team, he worked with all global IPs spread across various geos and proliferated IP-SoC-Platform Power Integrity methodology. He is currently a Platform Architect finding ways to improve and co-optimize system power delivery spanning across PCB, Package and Chip. He is evaluating platform PDN architecture, power rail merging, power management impact, IP/SoC PDN spec definition, decoupling strategy, and signal integrity impact on a future mobility product.     

Overall during his time at Intel, Vishram led or provided technical guidance on developing various new PI/SI methodologies that helped in spec development, optimization, area savings, Platform BOM cost reduction and product quality improvement. He had significant impact on different business units bottom line and certainly to the SI/PI community.

Vishram is an active member of the Technical Program Committee and serves as a co-chair for Track 11, covering power integrity in power distribution networks. This year at DesignCon, he is co-authored of the paper for the technical session, “Novel Isolation Scheme for Mitigating PDN Coupling.”

Vishram has received many awards in his field, including Divisional Recognition Award for his work on next generation memory technology enabling and specification (Power Integrity), Divisional Recognition Award for his contributions to noise mitigation for PDN in next generation single-ended multi GHz I/O interfaces, Divisional Recognition Award for developing on-chip PDN methodologies that saved cost be eliminating the pessimism margin in the design, and Divisional Recognition Award for co-optimizing across IP/SoC/Pkg/PCB to achieve cost reduction and power integrity for next generation differential speed I/O interface. He is an IEEE Senior Member, a Member of IEEE CPMT Technical Committee on Electrical Design, Modeling and Simulation (from 2008), and listed in Marquis Who’s Who in America: 2011-17.

His publications include authoring/co-authoring 10 online publications in Intel’s prestigious DTTC conference. Vishram is a co-author of the book, Power Integrity for I/O Interfaces: With signal integrity-power integrity co-design was published by Prentice Hall in October 2010. He also was a co-author of a paper which acquired DTTC’s best paper award and authored/co-authored 10 publications at Intel’s Joint Seminar on Signal and Power Integrity (JSSPI). He has authored/co-authored 18 publications in DesignCon, including 3 best paper awards and 3 finalists. 

Cast your vote for the 2018 Engineer of the Year by noon ET, January 12.

Steve Sandler

Founder and CEO, Picotest

Steve Sandler has been involved with power system engineering for nearly 40 years. Steve is the founder of, a company specializing in power integrity solutions including measurement products, services and training. He frequently lectures and leads workshops internationally on the topics of power, PDN, and distributed systems, and is a Keysight certified expert for EDA software. Steve Sandler frequently writes articles and books related to power supply and PDN performance and his latest book, Power Integrity: Measuring, Optimizing and Troubleshooting Power-Related Parameters in Electronics Systems was published by McGraw-Hill in 2014. He' was the recipient of the ACE 2015 Jim Williams Contributor of the Year Award for his outstanding and continuing contributions to the engineering industry and knowledge sharing. Steve is also the founder of AEi Systems, a well-established leader in worst case circuit analysis and troubleshooting of satellite and other high reliability systems.

With endless publications, consulting work and seminars around the world, Steve has selflessly shared his research findings and expertise. A nominator calls Steve a role model and truly an Engineer's Engineer.

Steve is the organizer, moderator, and undoubtedly will also be an active discussion participant in our Tuesday keynote panel, “SI/PI & EMI Challenges: Looking Ahead Through 2023.” He will be running the technical session, “40 GHz PCB Interconnect Validation: Expectations vs Reality” and the sponsored session, “Measuring and Interpreting Impedance for Power Integrity.” Steve will also be participating in the technical session, “Power Integrity for 32 Gb/s SERDES Transceivers.”

Steve is an active member of the DesignCon Technical Program Committee and reviews abstracts and papers for tracks 4 (system co-design), 11 (power integrity), and 13 (test & measurement).

Cast your vote for the 2018 Engineer of the Year by noon ET, January 12.

Yuriy Shlepnev

President and Founder, Simberian Inc.

Yuriy Shlepnev is President and Founder of Simberian Inc., where he develops Simbeor electromagnetic signal integrity software. He received M.S. degree in radio engineering from Novosibirsk State Technical University in 1983, and the Ph.D. degree in computational electromagnetics from Siberian State University of Telecommunications and Informatics. He was principal developer of electromagnetic simulator for Eagleware Corporation and leading developer of electromagnetic software for simulation of signal and power distribution networks at Mentor Graphics. The results of his research are published in multiple papers and conference proceedings.

Yuriy conceived and brought to market a state of the art electromagnetic field solver tool suite and is considered an expert in his field and regularly posts teaching videos.

Yuriy is active in the Technical Program Committee for DesignCon and serves at a co-chair for Track 14, modeling and analysis of interconnects. At DesignCon this year he will be running the technical session, “40 GHz PCB Interconnect Validation: Expectations vs Reality” and the Sponsored Session, “Measuring and Interpreting Impedance for Power Integrity.”

Cast your vote for the 2018 Engineer of the Year by noon ET, January 12.

By Engineers, For Engineers. 
3 days of technical content  spanning 14 tracks. New this year: Acquire an IEEE credit for every hour you spend at the conference. Learn more: DesignCon. Jan. 30-Feb. 1, 2018, in Santa Clara, CA. Register here for the event, hosted by Design News’ parent company UBM.
TAGS: Electronics
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