Newton, MA--Largely driven by hand-held telecommunications and portable PC applications, ICs and other electronic components are packing more punch into existing and smaller packages. But with smaller die sizes, increased component density, and more compact packages overall, designers have to consider not only physical effects coming into play in a component but the limits of its manufacturing process.
Take, as an example, Burr-Brown's (Tucson, AZ) 3.10 X 3.00-mm footprint, SOT-23 package, 1.45-mm high, introduced 10 years ago as a three-lead package holding discrete transistors. As with any component, volume production efficiencies have driven down costs, and advances in circuit design and manufacturing processes have boosted performance. The latest eight-lead version contains two complete devices, such as op amps.
According to Burr-Brown Strategic Planner Howard Skolnik, "The shrinking of integrated circuit die may require significant changes in the basic fabrication process, often with related changes in circuit design, packaging, and manufacturing. Improvements in wafer fabrication, including reduced defect density and sub-micron line widths, have advanced the ability to economically shrink the size of die and overall component dimensions." He adds, "If defect density is not lowered, reducing size will usually result in higher reject rates."
Test finesse. As smaller devices are produced, they must be tested--in high volumes and cheaply, according to Gary Carr, Hewlett-Packard Components Group (San Jose, CA) business development manager. In bringing HP's SC-70 package to market, "the tiny packages had easily deformable leads, and we had to negotiate a learning curve for high-volume handling and test," he notes (DN 8/3/98, p. 51). Testing requires good lead contacts, and force applied to the wrong spot sometimes bends leads. The solution: additional support on the package bottom. And "disciplined process control and training, as well as the latest in pattern-recognition and handling equipment allowed high-yield, repeatable assembly and test," Carr adds.
Reducing device feature size shrinks die dimensions and cuts the power required. Burr-Brown's Skolnik notes, "The smaller and shallower circuit diffusions lower capacitance. Thus less current maintains the same speed and less power is needed to perform an equivalent function."
But smaller feature size also lowers breakdown voltage, dictating a lower supply voltage. While, Skolnik notes, "in a purely digital component this does not necessarily imply a reduction in performance. Rather, it can mean higher speed and a further reduction in power consumption. However, with analog components, lower supply voltage can impose limitations on performance, including input and output voltage swing, resolution, and accuracy.
"Tiny packages force other compromises on the designer," Skolnik adds. "To attach the IC die to the lead frame of a SOT-23, the designer is forced to internally connect one of the die pins to the 'flag' or central area of the lead frame." This connection defines pin function, but causes the pin to take on different functions when used with various fabrication processes (N- or P- substrate, for example). "Therefore, designing pin-for-pin compatible replacement parts may be complicated in future product generations," he concludes.
And with diminutive packages, the smaller the surface area of the die and package, the more difficult to dissipate power. Die temperature increases, reducing performance and reliability. Thus, notes Skolnik, in products requiring higher power, heat transfer, not feature size, may be the limiting factor in package reduction.
Smaller still. As for the future, Skolnik notes new packaging schemes, such as chip-scale packaging (CSP), driving overall package size down to only slightly larger than the chip itself. Conventionally, an IC die is mounted in a case and bond wires connect IC terminals on its top, active surface to the package leads. With CSP, solder "bumps" are placed on top of the active surface terminals. This package is then soldered in the inverted position, directly to the PCB. He cites concern about taking this attachment technology into conventional PCB environments. Specifically: limited inspection capability and PCB flux residue that could contaminate the IC interface."
Are CSPs compatible with current industry processes? Yes, according to National Semiconductor (Santa Clara, CA), first to market with its 1.45-mm square Micro-SMD dual op amp. Key technologies, according to Doug Simin, senior product engineer, include a stress-absorbing passivation layer on the chip to which the solder bumps are attached. The other side of the package is encapsulated in an epoxy-type coating. "The customer just has to prep the board as with standard surface-mount components. Then pick-and-place and standard reflow soldering can be used," Simin says. And the surface-tension physics of the package and the presence of solder on both the board and bumps allow self-aligning of the packages during reflow. Offsets can be three times those for flip-chip (no board solder) processes.
With contacts between the board and package, x-ray, not visual, inspection is needed to verify connection integrity. John Thomas, national director of marketing for standard analog products, says prospective customers note this is not a concern, because "they already have the right equipment and assembly expertise in place."
Finally, Burr-Brown's Skolnik feels CSPs "are perhaps the end of the evolutionary line for packaged parts, with direct chip attachment to the circuit board being next."
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