Sign up for the Design News Daily newsletter.
Making Cache Coherent SoC Design Easier with Ncore™ IP from Arteris
Addressing System-on-chip complexity and future trends
April 3, 2024
1 Min Read
Sponsored by Arteris
As the number and variety of computing elements in SoCs grow, specific application areas require a tight connection of processing elements through coherency. Interconnect IP makes cache coherent SoC designs easier, saving 50+ person-years effort per project vs DIY solutions.
Explore the challenges in designing cache coherent SoC architectures. Understand the role cache coherency plays in maintaining data integrity across different cache levels. Learn about interconnect IP as a solution
The following themes are explored:
Growing SoC design challenges amid the complexity of multi-core processors, diverse processing elements, and on-chip communication.
Insights into all types of cache coherency and non-coherency and their relevance in optimizing performance across diverse processing elements.
A solution called Ncore Interconnect IP for cache coherent SoC designs offering true heterogeneous cache coherency, scalability, ISO 26262 certification.
You May Also Like
Editors' Choice
Jun 4 - Jun 6, 2024
Jun 4 - Jun 6, 2024
Innovation in automation starts here. Discover and collaborate on automation solutions that are revolutionizing the entire production lifecycle — from design to production to market — and sharpen your competitive edge. ATX South is part of IME South, a six-in-one expo offering the latest insights & solutions spanning medtech, packaging, automation, plastics, design, & processing.
Register Now