CPLDs Move to Chip Scale Packaging

Consumer demand for small equipment with long battery life seems unquenchable, so the need for compact, low-power devices continues unabated. Xilinx Inc. is responding with low-power CPLDs that provide chip scale packaging that trims space requirements while matching the prices of larger quad flat packs.

The San Jose, CA, supplier of complex programmable logic devices is expanding its CoolRunner-II family with chips that have an extra I/O bank that can be used to support voltage level translation and device interfacing.

Two new chips, the XC2C32A and XC2C64Aa, offer smaller packaging than discrete logic devices now used for level shifting, while also providing the potential to implement additional logic functions using extra programmable gates.

The parts employ micro lead frame packaging, which provides the size of chip scale packaging at lower costs than discrete parts. The 32-cell version comes in a 32-pin version that measures 5 x 5 mm, while the 48-lead, 64-cell part measures 7 x 7 mm. The 32 and 64 macrocell parts offer 21 and 37 I/O lines respectively.

The CoolRunner line is designed for low-power applications, using the company's proprietary RealDigital technology. The parts draw only 14 muA in the standby mode.

Voltage shifting can be implemented using standard I/O pin configurations, so programming files don't have to be altered. If these translations don't require all the programmable cells that are available, cells can be used for additional functions. Though voltage translation is a key target application, the parts can be used as extensions of standard products or ASICs. A clock doubler and clock divider enable the chips to run in many systems.

The digital cores run at up to 385 MHz. Pricing for the parts, which are available in lead-free packages, start at 85 cents. The parts can be programmed with the company's ISE software. Additional members of the line have up to 256 macrocells.

Xilinx Inc. http://rbi.ims.ca/3859-576