DesignCon Engineer of the Year Connects in the AI Era

The race to develop next-generation GPUs and other technology for generative AI, machine learning, and other high-speed computing applications is now proceeding at a breakneck pace as various players in the electronics industry seek to carve their niche in this booming area. But for Casey Morrison, Chief Product Officer and Co-Founder of Silicon Valley-based Astera Labs, AI has been on the company’s radar since the company started operating in 2017 out of a Silicon Valley garage.

Morrison is this year’s winner of the DesignCon Engineer of the Year award, given to an industry technology leader who has made significant contributions in engineering and new product advancements at the chip, board, or system level, with a special emphasis on signal integrity and power integrity.

Morrison won for his pioneering work in semiconductor-based, high-speed connectivity solutions, which have become particularly important for AI and high-speed computing. He was chosen over four other finalists who themselves are heavyweights in their respective fields, including: Scott McMorrow, Strategic Technologist for Samtec; Yuriy Shlepnev, President and Founder of Simberian; Bert Simonovich, Signal Integrity and Backplane Consultant for Lamsim Enterprises; and Ransom Stephens, Consulting Senior Scientist for BitifEye Digital Test Solutions GmBH.  

“This is a great honor to be recognized by the DesignCon community with whom I’ve been working for well over a decade,” said Morrison in an exclusive interview with Design News. "I consider each professional relationship I’ve built with vendors, partners, and customers to be a special accomplishment for me personally.”

Starting in Serdes

Morrison has long been in the trenches on high-speed signal interfaces. After graduating with an MSEE from the University of Florida, he started his career with Texas Instruments working on an engineering design team involved in Serdes and signal integrity. It was at Texas Instruments where he met Jitendra Mohan and Sanjay Gajendra. The three decided the time was right to strike out on their own and in 2017 started Astera Labs, focusing on semiconductor-based connectivity solutions for cloud and AI infrastructure.

Morrison, who as Chief Product Officer spearheads Astera Lab’s technology development, said the strengths of Mohan, Astera’s CEO, and Gajendra, Astera’s COO, complement each other well and have helped the company grow from a garage-based startup to a Santa Clara-based company that recently was honored with the Global Semiconductor Alliance Most Respected Private Company award.

Good Timing

Morrison and his team’s vision of AI’s future upward trajectory was a key part of the company’s growth. “We were convinced of the promise of AI back in 2017. We believed that AI models would grow large enough to be practical only at cloud-scale. We bet that an exponential growth in AI processing power would be constrained by a fundamental problem: connecting powerful compute elements at a massive scale to tackle large, distributed AI workloads. While many other companies focused on building accelerators with unprecedented computing power, we decided to address the problem of connecting all of them to deliver the full performance of an AI cluster.

Astera Labs’ product line includes its Aries PCIe/CXL Smart DSP Retimers, Taurus Ethernet Smart Cable Modules, and Leo CXL Smart Memory Controllers. When asked about the current buzz around CXL, Morrison said, “CXL is appealing in many respects. It’s a broadly supported industry standard; it utilizes a ubiquitous physical layer technology called the PCI Express PHY; and it enables one of the holy grails of cloud-scale computing: composable disaggregated infrastructure. CXL allows you to expand, pool, or share memory with greater bandwidth and capacity. The composability of a CXL-based fabric allows you to receive scale in a cost-effective manner.”

Morrison also noted that Astera Labs tries to resolve not only connectivity issues but also issues such as network and memory bandwidth. “Connecting AI processors together is only part of the problem. These GPUs need a lot of resources, too. That’s why we set out to develop product families to address network and memory connectivity bottlenecks,” he said.  

Collaboration Important

CXL and other connectivity standards have developed over the years through groups engaging in a lot of back-and-forth discussion weighing the pros and cons of proposed specs. “It is very much an art to weigh all these important factors,” he said. “There are many situations where there are diverse opinions on how a spec should evolve.” Morrison conceded while he has lost a few battles along the way, he emphasized the need to maintain a collaborative relationship with others to move a goal forward.

Morrison drew a parallel between some of this professional work with playing clarinet in the San Jose Symphony in his spare time. “You are just one cog in a wheel, and everyone needs to be in sync. The same is true with any team of engineers working on a project."

Giving Back

While Morrison has what many can consider a successful career, he has more goals in mind. One of them is to give back to the educational and technical community. “Someday I aspire to reconnect with the University of Florida, or with other local universities or high schools to mentor students or perhaps host info sessions on topics related to signal integrity, high-speed system design, or entrepreneurship. I would love to engage in that type of educational outreach and mentorship.”

Morrison has already made good on that promise. He is donating the $1,000 Engineer of the Year Award grant he received to the ECE department at the University of Florida.