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Satisfy Your Chiplet Craving at the Chiplet Summit

This must-attend event in Santa Clara will delve into all aspects of chiplet technology.

Spencer Chin

January 31, 2024

3 Min Read
Intel chiplet-based FPGA
Semiconductor suppliers such as Intel are turning to chiplets to package complex devices that traditional SoCs can no longer handle. Intel

At a Glance

  • The all-important issues of establishing chiplet infrastructure will be covered in keynotes and tech sessions.
  • Other sessions will cover design, testing, applications, and state-of-the-art chiplet R&D.

The information-rich content lineup at the Chiplet Summit February 6-8 includes several keynote discussions that will explore industry efforts to create a chiplet design and manufacturing infrastructure, a key hurdle in adopting the technology.

For instance, Brian Rea of the UCIe Consortium, an industry consortium promoting the UCIe (Universal Chiplet Interconnect Express) technology, will talk about enabling an open chiplet ecosystem at the package level. The UCIe standard is one of two chiplet interfaces, the other being the Bunch-of-Wires (BoW) from the Open Compute Platform Foundation.

Also touting an open chiplet model are Bapi Vinnakota and Cliff Grossner from the Open Compute Project. The speakers will talk about projects to standardize design models, establish third-party testing, define best practices for assembly, and create a standard high-performance, low-power die-to-die interface.

Francisco Socal and Mark Knight, both from Arm, will talk about the concept of reusable chiplets for heterogenous computing. The speakers expect new standards will help designers build reusable chipsets to integrate into multiple systems. The standards will extend the Advanced Microcontroller Bus Architecture (AMBA)’s on-chip Coherent Bus Interface (CHI) to a chip-to-chip (C2C) version suitable for connecting chip(let)-to-chip(let).

Several technical papers will further explore the chiplet interface debate. Proponents of the Universal Chiplet Interface Express (UCIe) from the UCIe Consortium and Bunch-of-Wires (BoW) from the Open Compute Platform Foundation will examine their interface models and how they address requirements for speed, high reliability, flexibility, and low power. They will discuss the development of nterface controllers, achieving interoperability, and developing models that allow designers to test different options.

Securing Multi-Die Systems

Asides from the chiplet ecosystem, there are other issues. In a session on chiplet design and security, two papers will explore the vulnerabilities for chipset-based designs at the chip or chiplet level. These security issues extend to the die-to-die interfaces, packaging, and other circuitry including power and clock distribution. Exacerbating the issue is the problem of chiplets originating from different manufacturers, processes, or substrates.

Using Chiplets in AI

Not surprisingly, chiplets are considered a prime candidate to house high-speed computing chips for demanding applications such as generative AI. However, many issues arise in using them in the quest for more processing power at the right price. A panel session titled “Chiplets Drive Top-Edge Leading Designs” will explore what needs to be done to make chiplets practical for generative AI. It will cover the need for new architectures and packages that can allow higher power ratings, more conductive area, and faster interconnections. Other issues include testing and integration and the availability of standardized chiplets to speed design and time-to-market.  

A related issue is power, since it must be distributed properly among chips with varying requirements and often high demands. One paper is these sessions, “Using Integrated Voltage Regulators in Chiplet Design,” presented by Empower Semiconductor, will discuss an advanced power management architecture in a compact single IC with no external discrete components. These devices can be used for traditional system power in space-constrained applications as well as integrated as a power chiplet into an SoC or chiplet-based architecture.

Chiplet Breakthroughs

Not surprisingly, the Chiplet Summit will also explore several emerging chiplet developments. A panel discussion titled, “The Next Great Breakthrough in Chiplets,” will explore the possibilities, These include combined packages that allow designers to co-optimize chiplets from the partitioning stage through integration and test.

Other possible advances could include standards that allow for portability of chiplets between applications, better test tools and interposers, interoperability testing, optical interfaces, and exchanges or chiplet stores that allow designers to readily find what they need from various sources.

About the Author(s)

Spencer Chin

Senior Editor, Design News

Spencer Chin is a Senior Editor with Design News, covering the electronics beat.

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