FPGA Players Up the Ante For Edge Computing, AI

The use of field programmable gate arrays has been on the upswing in recent years, and with the growth of artificial intelligence and edge computing, these versatile chips can offer advantages such as low power consumption and higher energy efficiency. In response, FPGA vendors are strengthening their product offerings.

For instance, Microchip, which several years ago unveiled its PolarFire FPGAs, has added nine new technology- and application-specific solution stacks to its growing collection of mid-range FPGA and System-on-Chip (SoC) support. The stacks span the industrial edge, smart embedded vision and edge communications.

The solution stacks for edge computing are particularly notable, according to Shakeel Peera, Vice President of Strategy for Microchip, in a recent interview with Design News. Peera noted that as the intelligent edge grows, key requirements for semiconductors in those applications include power efficiency, security and safety, thermal constraints, zero configuration failures, and real-time and flexible response.

The PolarFire FPGA intelligent edge solution stacks are highly tailored to specific technologies and vertical-market requirements and include detailed intellectual property (IP), reference designs, development kits with sample designs, application notes, demo guides and more.  The solutions and stacks for smart embedded vision, industrial edge applications such as motor control, and edge communications. Microchip’s PolarFire  devices create new configurable processing capabilities through hardened RISC-V core complexes in a fast FPGA fabric and they are playing an integral role as computer workloads move to the power-sensitive intelligent edge. Their capabilities will be extended with a roadmap to increased compute capability in ever-smaller and less costly industrial, IoT and other edge-compute products.

USB Functionality

Recently, Lattice, which has traditionally been strong in low power programmable FPGAs, unveiled its CrossLinkU™-NX FPGA family, reportedly the industry’s first FPGAs with integrated USB device functionality in their class. The FPGA consume up to 75% lower power vs similar FPGAs.

Other features of the CrossLinkU NX FPGA include two hardened 4-lane MIPI D-PHY transceivers at 10 Gbps per PHY, and up to 37 programmable source synchronous I/O pairs for camera and display interfacing. The FPGA comes in packages ranging from a 4 mm x 4 mm WLCS (0.4 mm pitch) to a 17 mm x 17 mm BGA (0.8 mm pitch).

The FPGAs feature hardened USB 2.0 and USB 3.2 functionality with speeds up to 5 Gbps. These FPGAs offer a low power standby mode with always on, and a complete set of reference designs.

Intel Expands Portfolio

Last month, Intel expanded its Agilex 3 FPGA portfolio. The Agilex 3 devices are targeted at applications such as system/board monitoring and management, video/vision, protocol expansions, portable imaging and displays, sensor fusion, drives, and robotic I/O expansion.

Intel also expanded its Agilex 5 FPGA E-Series, which are designed for embedded edge applications. According to the company, the E-Series FPGAs deliver up to 1.6 times better performance per watt compared to 16nm node competitors. Power capabilities are accomplished using the second-generation Intel® Hyperflex™ FPGA architecture combined with Intel 7 process technology, where transistors are optimized for performance per watt. Intel will begin broad market shipments of E-Series engineering samples to customers in the first quarter of 2024, along with general access of design software.

In addition, Intel said its Agilex® 7 FPGAs with R-Tile are now shipping CXL IP with 2.0 features in volume: Launched in May 2023, the Intel Agilex 7 FPGAs with the R-Tile chiplet deliver leading technology capabilities with 2 times faster PCIe 5.0 bandwidth as well as 4 times higher CXL bandwidth per port when compared to other competitive FPGA products, according to the company. The configurable and scalable architecture of Intel Agilex 7 FPGAs enables customers to quickly deploy customized technology to reduce overall design costs and development processes and to expedite execution to achieve optimal data center performance.

Spencer Chin is a Senior Editor for Design News covering the electronics beat. He has many years of experience covering developments in components, semiconductors, subsystems, power, and other facets of electronics from both a business/supply-chain and technology perspective. He can be reached at [email protected].