Die-Level IP Integration: Why Your Next Design Could Be Via Compound Semiconductors on CMOS

DN Staff

July 9, 2015

2 Min Read
Die-Level IP Integration: Why Your Next Design Could Be Via Compound Semiconductors on CMOS

Packaged ICs comprising a single die in standard CMOS silicon technology will soon become less standard if the Defense Advanced Research Projects Agency (DARPA) and its commercial partners have their way.

Chasing Moore's law is increasingly costly, especially for low-volume applications. As a result of unfavorable value propositions (real or perceived) in sub-28 nm process nodes, die shrinks for many medium- and low-volume products may no longer be economical, despite the continued market needs for "smarter, faster, smaller."


DARPA is working to enable commercial-grade Diverse Accessible Heterogeneous Integration (DAHI). In parallel with this program, DARPA is supporting the integration of multiple dies with different functions (logic, memory, analog, MEMS) in a single IC package.

DARPA "... is developing transistor-scale heterogeneous integration processes to intimately combine advanced compound semiconductor devices, as well as other emerging materials and devices, with high-density CMOS technology."

With sub-28 nm silicon offering significant opportunities for SoC-type integration, why the need for DAHI's kind of heterogeneous integration? One answer is that it creates the opportunity for die-level IP integration.

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In one example, DARPA is working to heterogeneously integrate indium phosphide "chiplets" with trailing-edge CMOS (130 nm process node; 200 mm wafers) in order to achieve advanced process node performance without the advanced process node cost.

This combines the main strength of CMOS silicon, high levels of integration, with the high electron mobility benefit of indium phosphide, giving InP-based designs the edge in transistor speed compared to CMOS.

While the DAHI efforts are ideal for high-value applications, compound semiconductors are unlikely to become an alternative for implementing heterogeneous functions in low-end Internet of Things devices. Instead, multi-die silicon device packaging technology is more likely to fit the bill.

Historically, EDA vendors and IC designers were only concerned about implementing their ideas in a single die and saw IC packaging as a simple, almost negligible, manufacturing step.

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