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DesignCon Keynote: Silicon Photonics Chips Key for Data Centers

Photonics expert John Bowers says the continued emergence of integrated silicon photonic chips will drive high-bandwidth future data centers.

Spencer Chin

April 6, 2022

3 Min Read
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John Bowers, Fred Kavli Chair of Nanotechnology, University of California, Santa Barbara, discusses silicon photonics at DesignCon.Image courtesy of Spencer Chin

The long-standing image of data center infrastructures with miles of copper cables will gradually give way to more compact data centers with optical-based interconnects using co-packaged photonics devices on silicon substrates, according to John Bowers, Fred Kavli Chair of Nanotechnology, University of California, Santa Barbara.

Speaking during a keynote session at the DesignCon 2022 Conference and Exposition in Santa Clara on Tuesday, Bowers said optical interconnects would be the only way to efficiently transmit huge amounts of data, given the massive amounts of information data centers will be processing, thanks to trends such as artificial intelligence (AI).

“Copper traces are lossy at high speeds, often losing as much as 20 dB at the chip’s edge,” Bowers said. “We want to limit the loss to no more than 3 to 4 dB.”

As data centers scale up in processing power, the issue becomes more of bandwidth vs I/O. Bowers noted that while bandwidth needs were doubling every two years, the amount of I/0 would take three to four years to double, creating an obvious bottleneck in data handling capacity. This in turn resulted in increased packaging and signal integrity complexity.

Silicon and Photonics Match

To meet ever more robust data center needs, Bowers said there was a need for larger, more complex chips. With traditional copper unable to keep up with those signal needs,  engineers have turned to photonics. While research has been going on for many years, there has been considerable progress in this area over the past decade, particularly the past five years or so.

Related:Integrated Silicon Photonics Driving High-Speed Optical Interconnects

The ability of photonics to efficiently carry large amounts of data, compared to copper, has not been in question. The issue has been scaling up the packaging and substrate technologies to production reliably and at lower costs. This would enable OEMs to mass produce photonics assemblies in the quantities needed for data centers.

Bowers said that materials such as InP (Indium Phosphide) and GaAS (Gallium Arsenide) have been difficultꟷand expensiveꟷto scale up to the volumes needed for efficient mass production. After years of research, engineers found that a familiar materialꟷsilicon─could be counted on to provide the substrate platform for photonics parts.

“Photonics can use 45-nm silicon fab processes, which are several generations old,” Bowers said. He added that companies such as Intel, Cisco, Juniper, NTT, and Avago have been doing work in silicon photonics, as well as silicon foundries such as Tower Semiconductor.

Related:Two Myths About Silicon Photonic Chips

Bowers pointed to an example of a co-packaged optics Ethernet switch in demonstrated in 2020. The switch contained 16X lasers coupled to 16X 106 Gbps PAM4 ring modulators, handling 1.6 terabits per second bandwidth.

Continued advances in integration are expected to lead to further advances. By next year, Bowers expects silicon photonics advances to enable product bandwidths exceeding 1 terabits per second per fiber. Technology improvements will enable the development of silicon photonics chiplets in package (SCIP), which in turn would reduce parts count.

Beyond chiplets, Bowers foresees co-packaged optics using heterogeneous integration of multiple dies on a common package substrate.

Spencer Chin is a Senior Editor for Design News covering the electronics beat. He has many years of experience covering developments in components, semiconductors, subsystems, power, and other facets of electronics from both a business/supply-chain and technology perspective. He can be reached at [email protected].

About the Author(s)

Spencer Chin

Senior Editor, Design News

Spencer Chin is a Senior Editor with Design News, covering the electronics beat.

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