Vote for the 2022 Engineer of the Year

The time has come for the engineering community to cast your vote for the DesignCon 2022 Engineer of the Year. This award is given out each year during the DesignCon event and seeks to recognize the best of the best in engineering and new product advancements at the chip, board, or system level, with a special emphasis on signal integrity and power integrity.

Editors of Design News and the staff of DesignCon would like to offer hearty congratulations to the finalists. For this year’s award, the winner (or his/her representative) will be able to direct a $1,000 donation to any secondary educational institution in the United States. The details on each nominee are below as provided in their published biographies and by the person/s who made the nomination. Please cast your vote by following this link.

Voting closes at noon Pacific Time on March 11. The winner will be announced at DesignCon 2022, April 5-7 at the Santa Clara Convention Center, Santa Clara, CA.

The four finalists for the 2022 DesignCon Engineer of the Year Award are (click each name to see finalist’s bio and community activity):

Related:DesignCon 2022 Engineer of the Year Nominations Are Now Open

Cast your vote for the 2022 Engineer of the Year

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Scott McMorrow, CTO, Samtec

Scott McMorrow currently serves as CTO for Samtecs Signal Integrity Group, Inc. As a consultant for years too numerous to mention, Scott has helped many companies develop high-performance products while training signal integrity engineers.

Scott started Samtec’s webinar series gEEk spEEk, providing virtual engineering learning. Scott also works on Samtec’s Twinax technology, pushes EDA companies to focus on signal integrity, developed advanced crosstalk analysis and power delivery methodology. He has related RF EDA to signal integrity (meshing, boundary conditions, computational space, etc.) and has a long history of supporting, speaking at, and writing for DesignCon.

Scott received a DesignCon 2021 Best Paper Award for his work on the paper “A Case Study in the Development of a 112 Gbps-PAM4 Silicon & Connector Test Platform.”

Richard Mellitz, Distinguished Engineer, Samtec

Richard Mellitz is presently a Distinguished Engineer at Samtec, supporting interconnect signal integrity and industry standards. Prior to this, he was a Principal Engineer in the Platform Engineering Group at Intel. Richard was a principal member of various Intel processor and I/O bus teams including Itanium, Pentium, PCI Express, SAS, and Fabric (Ethernet, IB, and proprietary). Additionally, he has been a key contributor for the channel sections IEEE802.3 backplane and cabling standards, and for the time domain ISI and return loss standards for IEEE802.3 Ethernet, known as COM (Channel Operating Margin) and ERL (Effective Return Loss), which are now an integral part of Ethernet standards due to Rich’s leadership.

Related:DesignCon 2022 Locks in High-Caliber Keynote Speaker Lineup for April Event

He founded and chaired an IPC (Association Connecting Electronics Industries) committee delivering IPC’s first PCB loss test method. Prior to this, Rich led industry efforts at IPC to deliver the first TDR (time domain reflectometry) standard which is presently used throughout the PCB industry. Richard holds many patents in interconnect, signal integrity, design, and test. He has delivered numerous signal integrity papers at electronic industry design conferences.

Richard contributed to three DesignCon 2022 papers, see more information in the online agenda.

Steve Sandler, Founder, Picotest.com

Steve Sandler has been involved with power system engineering for more than 40 years. Steve is the founder of PICOTEST.com, a company specializing in power integrity solutions including measurement products, services, and training. He frequently lectures and leads workshops internationally on the topics of power, PDN and distributed systems and is a Keysight certified expert for EDA software. Steve frequently writes articles and books related to power supply and PDN performance and his latest book, Power Integrity Using ADS was published by Faraday Press in 2019. Steve founded AEi Systems, a well-established leader in worst-case circuit analysis and troubleshooting of high-reliability systems.

Steve is a long-time and very active member of the DesignCon Technical Program Committee, and received a DesignCon 2017 Best Paper Award for his paper, “Characterizing and Selecting the VRM.”

For DesignCon 2022, Steve is planning to speak at a tutorial, present a paper, and participate in a panel. You can see the session details on the online agenda.

Lambert (Bert) Simonovich, Founder, Lamsim Enterprises

Lambert (Bert) Simonovich graduated from Mohawk College of Applied Arts and Technology, Hamilton, Ontario Canada, as an Electronic Engineering Technologist. Over a 32-year career, working at Bell Northern Research/Nortel in Ottawa Canada, he helped pioneer several advanced technology solutions into products. He has held a variety of engineering, research, and development positions, eventually specializing in high-speed signal integrity and backplane design. In 2009, he founded Lamsim Enterprises Inc., where he continues to provide innovative signal integrity and backplane solutions as a consultant. He has authored several publications and holder of two US patents.

In addition to being a senior member of IEEE, he currently serves as a member of DesignCon's Technical Program Committee, EDICon's Technical Advisory Committee, and Signal Integrity Journal's Editorial Advisory Board. His current research interests include high-speed signal integrity, modeling, and characterization of high-speed serial link architectures. His most notable modeling achievement is the development of the "Cannonball-Hurry" conductor roughness model used in several electronic design automation (EDA) software tools.

Bert has received Best Paper Awards for his 2019 paper “PCB Interconnect Modeling Demystified,” and the 2018 paper “A Causal Conductor Roughness Model and its Effect on Transmission Line Characteristics.”

Cast your vote for the 2022 Engineer of the Year. Voting closes at noon Pacific Time on March 11.