While automotive applications are not memory manufacturer Micron’s largest end-market, that sector has become increasingly important as autonomous and electric vehicles continue to help drive up the amount of electronics content in these applications. To this end, Micron has beefed up the design of its LPDDR5 memory parts to achieve the International Organization of Standardization (ISO) 26262 Automotive Safety Integrity Level (ASIL) D certification for those parts.
The certification is based on the 1α (1-alpha) process node and validates that LPDDR5 memory meets strict functional safety standards and helps position Micron to team with automakers to enable innovations that will unleash full autonomy in intelligent vehicles.
“We have spent the last few years trying to determine all events where memory could fail,” said Robert Bielby, Senior Director of Automotive System Architecture for Micron. “Vehicles that drive themselves must be as free of memory errors as possible.”
Bielby noted that the challenge for memory in vehicles is to deliver increasing levels of performance at reduced power. At the same time, the high-volume nature of automotive applications requires that vehicle memory needs to scale in density at continuously lower costs while employing advanced semiconductor process technologies. To this end, Micron has contended that memory products for safety applications should be consistently classified as Class III complex semiconductors per the guidance per ISO 26262 standard, the same categorization assigned to processors, SoCs and GPUs.
The ISO 26262 standard defines various safety levels in a risk-classification system from A through D. Systems with an A level rating (such as rear lights) represent the lowest degree of risk with a failure while systems with a D level (such as anti-lock brakes) represent the highest risk. To Micron, ensuring that vehicle hardware systems meet standards for mitigating safety risks is paramount because component-level and system-level complexity for many emerging Advanced Driver Assistance Systems (ADAS) platforms is equivalent to or greater than those in data centers.
To make the LPDDR5 DRAM ASIL-compliant, Micron designed onto the chip safety measures that provide advantages to system designers beyond typical JEDEC standard products. These advantages include fault detection capabilities that can meet industry ASIL-D random hardware error metrics.
In addition, Micron engineered into the DRAM safety features that enable significant power reductions, performance improvements, memory efficiency and board area savings over traditional safety implementations and strategies that are based upon employing in-line ECC or redundancy to achieve requisite system level safety targets. The ASIL-D compliance is similar to that applied to other Class III complex devices, such as processors, SoCs and GPUs.
Micron has also strengthened its quality control by offering extensive safety analysis collateral for existing QM-grade products to support customer integration, and an extensive global network of automotive system labs near many customer locations that deliver remote, virtual lab support.
According to Bielby, the LPDDR5 DRAMS are the first of Micron’s memory products to fully comply with ASIL-D requirements. The company will gradually redesign its other memory products to be ASIL-D compliant.
Spencer Chin is a Senior Editor for Design News covering the electronics beat. He has many years of experience covering developments in components, semiconductors, subsystems, power, and other facets of electronics from both a business/supply-chain and technology perspective. He can be reached at [email protected]