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Enhance Your Engineering Know-How at DesignCon

Here’s a sampling of important technical sessions and panel discussions at the upcoming DesignCon Show in Santa Clara.

Spencer Chin

January 10, 2024

4 Min Read
DesignCon 2024
DesignCon 2024 provides engineers the opportunity to learn about the latest engineering trends and technologies in a single setting.DesignCon

At a Glance

  • The upcoming DesignCon Show in Santa Clara, Calif., is a treasure trove of information and education for design engineers.
  • Topics span areas such as vehicles, signal integrity, packaging, test and measurement, and AI.

The annual DesignCon Conference and Exhibition is scheduled to take place January 30 through February 1st at the Santa Clara Convention Center in Santa Clara, Calif. For engineers, this is the perfect opportunity to learn about the latest trends and developments in key areas affecting electronics design, whether it be signal integrity, board design, semiconductor packaging, vehicle electronics, artificial intelligence, and machine learning, to name just a few areas.

While the DesignCon site should be the first place engineers go to learn about and register for this important show, here is a random collection of interesting sessions worth attending.

The Role of Chiplets

Without a doubt, many engineers are showing interest in chiplets to help design the electronics systems of the future. On Tuesday, January 30th, from 4:45 to 6:00 pm, there’s a panel session titled, “Chiplets in Consumer Electronics & Infrastructure: Opportunities & Challenges.” The session will talk about the advantages of chiplets such as mix-and-match capability, IP reuse, and faster time-to-market. Several discussed applications include AR/VR compute silicon, wrist wearable, and display systems. The session will examine 2D, 2.5D, and 3D technologies as well as signal and power integrity, testing and security, and EDA tools.

Test & Measurement For Vehicles

Once again, DesignCon’s Test on Wheels panel will look at the unique signal integrity challenges encountered in the difficult vehicle environment. Also taking place Tuesday, January 30th from 4:45 to 6 pm, the session will look at the progress in bringing SERDES compliance test suites (CTS) chipsets, and initial test solutions.  This year's panel will focus on lessons learned by the people who design the SERDES and interconnect technology, define the standards that promise component interoperability, and create the test instruments─what has been leveraged from established HSS standards like IEEE802.3 (GbE), PCIe, and USB, and what still needs work.

Software-Defined Vehicles

Staying in the vehicle realm, the growth of software-defined vehicles remains a pronounced trend. On Wednesday, January 31st, from 9:00 to 9:45 AM, a session titled “Trustworthy Software-Defined Vehicles” will discuss this technology's potentially catastrophic security risks. This talk will discuss the key requirements, standards, and techniques for building trustworthy software-defined vehicles through a layered data-centric architecture that protects the data in motion, ensuring that only authorized data is shared among software components. The talk will describe how the desired level of system reliability, resilience, and ASIL level can be achieved while adhering to safe software development practices.

Data Centers and AI

With artificial intelligence (AI) increasingly impacting engineering design, one of the big concerns is the power needs for supercomputers and data centers. On Wednesday, January 31st from 4:00 to 5:15 pm, a panel session titled, “The Impact of Data Center & AI Growth on SI/PI (signal integrity/power integrity) Engineers,” discusses the challenge of engineering higher density, higher efficiency power modules. The session will examine the difficulty of reaching target impedance levels below 30 microohms, as well as the consequent thermal challenges. The panelists will look at the challenges of analyzing factors such as crosstalk, EMI, and the di/dt of the dynamic current.

PAM-4 Signaling

PAM-4 has been a popular topic at recent DesignCon shows as more engineers seek to utilize this modulation technique to double a network’s data range. Not to disappoint, there will be several sessions at this year’s show looking at various aspects of implementing PAM-4. On Wednesday, January 31st at 9 AM, a session titled, “Enhancing End-to-End 224G Systems By Optimizing Conductors for Meta Performance,” provides a comprehensive analysis of the performance, design trade-offs, and practical considerations to enhance the End-to-End 224Gbps Ethernet Channel performance, by the integration of metaconductors on package technology. The integration of alternating coplanar structures composed of Copper (Cu) and Cobalt (Co) offers distinct advantages, particularly in reducing the attenuation of single-ended and differential transmission lines. This characteristic has significant implications for high-speed end-to-end electrical systems and their associated equalization architecture. 

EMI and Crypto/Information Devices

With the rise in cryptography devices that can reveal secret information, there’s the need for power delivery networks to maintain hardware security and withstand potential EMI attacks. On Thursday, February 1st at 2 PM, a session titled, “EMI and Intentional EMI Attacks Against Power Delivery Network of Crypto/Information Devices,” looks at what happens when EMI radiation is applied to the power delivery network of crypto and information devices. Also, IEMI (intentional EMI) is induced to cause malfunctioning. The technical paper will reveal the frequencies where crypto devices are vulnerable.

About the Author(s)

Spencer Chin

Senior Editor, Design News

Spencer Chin is a Senior Editor with Design News, covering the electronics beat.

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