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Home>CEC Archive>CEC Semester Twelve 2017

FPGA Programming

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Highlights
September 13 – Day 3 – HDL
Jul 03, 2018
Algorithms for FPGAs are specified via a Hardware Description Language (HDL).  We will look at a couple of these...
September 14 – Day 4 – Synthesis and Layout
Jul 03, 2018
Once a design has been developed in a HDL and tested and verified, we need to lay it out on the chip.  This is analogous to layout for ASICS but it is not as complicated since we are using an existing regular structure.  Layout is important...
September 15 – Day 5 – Programming the Chip
Sep 15, 2017
Now that we have an algorithm developed, debugged and laid out in our design tolos we are ready to transfer that to the FPGA chip and run our algorithm there.  We will also discuss the process of reprogramming the chip during operations and will...