FPGA Programming

The flow of design tasks will be somewhat dependent on the FPGA vendor and tool set, but there are some general steps that are generally followed.  We will start with these general steps and then look at some of the particular vendors.  There are...

Algorithms for FPGAs are specified via a Hardware Description Language (HDL).  We will look at a couple of these, VHDL and Verilog.  Many design tool sets support both.  The one you use will depend on standards and skills available in your shop. ...

Once a design has been developed in a HDL and tested and verified, we need to lay it out on the chip.  This is analogous to layout for ASICS but it is not as complicated since we are using an existing regular structure.  Layout is important...

Now that we have an algorithm developed, debugged and laid out in our design tolos we are ready to transfer that to the FPGA chip and run our algorithm there.  We will also discuss the process of reprogramming the chip during operations and will...