Austin, TX -Depending on whose figures you accept, the volume of data transmitted over the Internet doubles every three to six months. That means manufacturers must constantly increase the capacity of their routers, optical transceiver modules, digital crossconnects, and other machines. But while the data flow grows exponentially, the machines can't. Packing more circuitry onto cards is the standard response, but that increases the danger of interference and raises power consumption, both of which can degrade system accuracy.
Envisioning a series of physical layer ICs for high-speed fiber optic communications systems to address the problems created by ever-increasing data volumes, engineers at Silicon Laboratories began work on one of the key building blocks of high-speed optical data communications systems: The SI5020 clock and data recovery (CDR) IC.
In such systems, the optical signals, which originate as electrical signals, need to be converted back to electrical signals to be recognizable by end use devices. But transmissions over long stretches of optical fiber degrade the signal, and it is the job of the CDR to reconstruct and synchronize these signals. Timing is a key factor in the reconstruction, hence the term "clock."
"The receiving station has to be able to extract the original data sequence from the incoming data stream and resynchronize the data to the original timing," says Jim Templeton, vice president and general manager of Silicon Labs' Optical Networking Division. "The accuracy with which it performs this function is critical to the success of the system."
Silicon Labs' proprietary DSPLL technology helps the Si5020 clock and data recovery integrated circuit meet stringent specs for jitter -- the degree of uncertainty in timing -- that can be present in a component or system.
The CDR project was also a good fit with the company's previous technology. OC-48, one of today's higher end optical communications applications specifications, provides for data streams at a rate of 2.5 Gbits per second. "To run effectively at these speeds, the CDR needs a very high quality VCO (voltage controlled oscillator), which we had already created for our RF synthesizer for cell phones and other wireless devices. It turns out that the critical spec for the cell phone product is phase noise, and phase noise relates to jitter, which would be the critical SONET spec for our new family of high-speed physical layer ICs," says Templeton. SONET is an acronym for synchronous optical network, the dominant protocol for optical data traffic.
"We already had a high degree of confidence that our VCO problem was solved before we started designing the CDR," says Templeton. "The real challenge was to generate a loop filter that was desensitized to outside interaction, whether that was cross-coupling from other ICs, magnetic radiation, changes in temperature, or changes in power supply, and that really was where we spent 70-80% of our design effort."
Insurmountable. Small wonder, as the challenge seemed all but insurmountable with conventional design approaches, in large part because of the highly interactive nature of the physical layer environment.
"Initially, we interviewed 24 potential users, and all were concerned with the issues of power, size, accuracy and ease of use. It became apparent, though, that the issue of ease of use, which we define as the ability to attain and maintain the required performance over time, temperature, and voltage, was perhaps the hardest problem to solve. What we realized was, the problem is always related to the sensitivity of the external loop filter component, part of the phase lock loop (PLL), a key component in timing accuracy," explains Templeton.
Engineers first considered putting the loop filter components, which are typically resistors, capacitors, and ferrite beads, inside the package, or inside the die, and desensitizing it. But that led to a very large CDR housing a PLL that was still sensitive to outside interaction. "Our designers refused to accept that this problem was unsolvable. Rather than bury this sensitive node inside the package, they eliminated it by digitally synthesizing its loop filter function," recalls Templeton.
They called their solution DSPLL(TM)(a combination of digital signal processor and phase locked loop). It uses a DSP algorithm to process the phase detector error term and generate a digital control value to adjust the frequency of the VCO. Because external loop filter components are not required, sensitive noise entry points are eliminated, making the DSPLL less susceptible to board-level noise sources and boosting accuracy by greatly enhancing the Si5020's SONET jitter compliance.
The Si5020 boasts other benefits as well, such as size: measuring just 4x4 mm, the device is five times smaller than its nearest competitor, and the lack of external loop filter components provides additional space savings. It also requires 50% less power than similar CDRs.
Also noteworthy is the fact that the Si5020 was designed completely in CMOS. This is in keeping with Silicon Labs' design philosophy. It allowed a greater amount of signal processing to be used than would have been feasible with Silicon Germanium or bipolar processes, with consequent gains in size reduction and accuracy.
Contact Jim Templeton, Silicon Labs; 4635 Boston Lane, Austin, TX 78735; Tel: (514) 416-8500; Fax: (512)416-9669; E-mail: [email protected]