Where Will Chiplets Head in 2025?Where Will Chiplets Head in 2025?
High-performance computing needs expected to drive growth of multi-die packages, particularly 3D.

For the past few years, chiplets have held the promise of giving design engineers the flexibility to package multiple chips and handle diverse technologies, but issues such as standards, production infrastructure, and testing have been obstacles. One industry insider believes there will be measurable progress this year resolving these issues, particularly as the high-perfomance computing needs dictate more robust, flexible packaging solutions than traditional monolithic system-on-chip approaches.
In an interview with Design News, Michael Posner, Vice President of Product Management at Synopsys, predicts that as much as half of the new applications in high-performance computing will involve multi-die designs, which include chiplets.
“For a number of years, multi-die designs were reserved for those with specialized needs as well as sufficient budget,” said Posner. He added that much of the demand will come from 3D stacked multi-die solutions as users seek more space-efficient and higher performing alternatives to traditional monolithic chips.
According to Posner, AI and machine learning will be a key driver of 3D multichip solutions as those applications requiring a lot of processing power. “You cannot generate that amount of processing power in a traditional monolithic package. You need stacked and multichip packages.”
Posner told Design News that major semiconductor suppliers and contract manufacturers are ramping up their production capability for chiplets, which will eventually drive down costs. He added that Synopsys is working with many of these companies to produce a more streamlined design-to-production strategy that accounts for key steps such simulation, verification, and testing.
Testing remains a key challenge in developing multi-die packages, Posner said Synopsys is trying to use a hierarchical test method to test multi-die packages.
One factor that is helping with chiplet development is the rapid adoption of the UCIe (Universal Chiplet Interconnect Express) standard, an open chiplet interconnect standard that has helped to create a much-needed chiplet ecosystem governing many key aspects of chiplet development. Posner expect UCIe to account for the majority of chiplet engagement opportunities.
Chiplet Summit is here
Posner’s company, Synopsys, will be among the many companies giving presentations at the Chiplet Summit, the electronic industry’s key conference for chiplet education and information, being held at the Santa Clara Convention Center in Santa Clara, Calif., from January 21 through 23. Abhijeet Chakraborty, Vice President of Engineering at Synopsys, will deliver one of the initial presentations on Wednesday, January 22 at 10:10 am titled, not surprisingly, “Accelerating AI Chip Development with 3D Multi-Die Designs.” The talk will explore high bandwidth communications, 3D-enabled IP, and methods to achieve seamless continuity from 2D to 3D as approaches that are enabling the production of multi-die designs
Here is a sampling of other keynote sessions at the Chiplet Summit worth checking out.
Scaling Connectivity for Chiplet-Based AI Systems
In this Wednesday, 10:50 am keynote, Tony Chan Carusone, CTO at Alphawave Semi, will discuss chiplet-based designs as the key to scaling AI compute performance and connectivity. Carusone will show how chiplet designs allow for both scale-up, where chiplets enable more processing power in a single system, and scale-out, where interconnected systems do more as a unit. Carusone will also look at how optical connectivity, also facilitated by chiplets, offers high-speed data transmission with lower power consumption that is required to handle massive data loads.
Testing Chiplets
As no discussion on chiplets would be complete without a look at testing issues, Nitza Basoco, a technology and market strategist at Teradyne, will deliver a presentation Wednesday at 12 noon titled, “The Right Testing Strategy Can Save Designs,” where she discusses the urgency needed to develop a testing methodology that tests dies earlier in the process and gets rid of bad dies as soon as possible to control costs and scheduling.
Acclerating Chiplet Startups
While many of the presentations at the Chiplet Summit deal with technical and infrastructure issues, the potential growth of the sector is also attracting eager startup companies. Wednesday at 11:20 am, NIck Kepler, COO at Silicon Catalyst, will briefly discuss his firm’s work to partner with early-stage and incubator companies developing semiconductor solutions. Silicon Catalyst is built on a comprehensive coalition of in-kind and strategic partners to dramatically reduce the cost and complexity of development. The incubator/accelerator supplies startups with access to design tools, silicon devices, networking, and a path to funding, banking and marketing acumen to successfully launch and grow their companies’ novel technology solutions.
For more information on the Chiplet Summit, go here.
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