When Will the Automotive Industry Adopt Multi-Die Designs?When Will the Automotive Industry Adopt Multi-Die Designs?

The compute requirements of next-generation software-defined vehicles (SDVs) are growing exponentially, with customers demanding smartphone-like entertainment experiences as well as semi-automated driving capabilities. As Moore’s law slows down, the required compute performance pushes the size of commercially available monolithic SoCs to the limit of what is technically and economically viable.

Moreover, with the desired convergence (fusion) of advanced driver assistance systems (ADAS), in-vehicle infotainment (IVI), and other central functions into a single, integrated high-performance compute platform, the dependence on very few semiconductor vendors (vendor lock-in) concerns most OEMs. OEMs seek flexible semiconductor solutions, which they can scale along their vehicle portfolio from entry-level to premium-level cars, ideally keeping the same core compute architecture to avoid software porting while allowing for hardware scalability to the respective software workload.

Multi-die design, which is already state-of-the-art in the high-performance computing, AI, and data center domains, is being discussed in the automotive industry.

Chiplet program

Companies around the globe have come together to work towards a unified, standard process to ease the shift to muti-die designs for the automotive market. One example is the imec Automotive Chiplet Program (ACP). In a recent announcement, imec announced that Synopsys, among others, are the first that have committed to join its Automotive Chiplet Program (ACP), which brings together stakeholders from across the automotive ecosystem to evaluate which chiplet architectures and packaging technologies are best suited to support car manufacturers' specific high-performance computing and strict safety requirements, while striving to extend the benefits of chiplet technology – such as increased flexibility, improved performance and cost savings – to the entire automotive industry.

Related:Chiplets Make Case for More Apps

Automotive OEMs are aware of multi-die architecture and are assessing its advantages for automotive applications. Their vision is to integrate multiple heterogeneous or homogeneous dies in a single package, similar to electronic control units (ECUs) today, which comprise multiple monolithic SoCs on a printed circuit board (PCB) in a much smaller form factor and lower power footprint. Connecting the dies (also called chiplets) with dedicated die-to-die interfaces, such as the Universal Chiplet Interconnect Express (UCIe), consumes less power compared to traditional chip-to-chip connections. OEMs are looking to combine heterogeneous chiplets from different vendors to create optimized, modular, and scalable central compute platforms for their future ADAS and IVI needs.   

Related:Cheeky Chiplets Meet Super NoCs

Cost and standards remain hurdles

But as automotive OEMs and Tier 1s explore the use of multi-die design, they face several challenges. Developing a multi-die design is complex, requiring the right expertise and resources. It is too costly to be carried out by one automotive company alone. In addition, creating an open chiplet ecosystem would require standardizing the overarching architectural structure and the underlying die-to-die connectivity, which is way beyond what available die-to-die-interface standards, such as UCIe, define today. While this dilemma is understood and might be solvable through smart industry consortia and standardization efforts, two challenges remain:

 Levels of autonomy

The six levels of autonomous driving have each entailed different types of chips. While the lower levels can be handled with advanced microcontrollers, Level 2+ onwards requires complex SoCs with a mix of high-performance CPUs, AI accelerators, DSPs, and GPUs. Level 3 operates with a much broader and higher resolution sensor set and requires orders of magnitude more compute power than Level 2. Single-chip Level 3 solutions are available in the market, but require highly optimized AI and single instruction, multiple data (SIMD) hardware accelerators, tailored exactly to the software algorithms running on them. Different OEMs have different algorithm strategies and might require more flexibility regarding the hardware acceleration technologies available on such SoCs. Level 4 again requires more compute power than Level 3, clearly challenging what can be done on a monolithic SoC in an economically viable way.

Synopsys expects chiplets to thrust multi-die semiconductor packages into the spotlight for helping automotive OEMs meet the needs of next-generation automotive systems (Synopsys)

Two different conceptual approaches are being contemplated in the market today:

Of the two, the latter concept has a lot of merit to satisfy the industry’s ultimate desire for a scalable, combined (fused) ADAS/IVI central compute platform for future SDV generations.

Automotive benefits

For the semiconductor industry, the multi-die design approach is a paradigm shift that can enable a new wave of growth. In areas like PCs and data centers, multi-die designs are already being used. Obviously, these applications do not face the severe environmental challenges that automotive encounters.

From an architectural point of view, SoC architects will love multi-die designs, since they essentially eliminate the reticle size limit for their design. They still need to be smart about how to split the SoC into chiplets. Moreover, while the die-to-die interfaces are short distance, high speed, and very low power compared to, say, PCIe, they certainly need to be considered when properly planning for performance, data throughput and latency.   

Compared to large monolithic SoCs, a multi-die design offers the flexibility of mixing and matching dies in different process technologies to optimize for overall power, performance, and area (PPA). Depending on the vehicle subsystem requirements, not every die must be from the most advanced node. This is beneficial, especially considering the rising costs of fabricating silicon at deep submicron process nodes. Their modularity and scalability make it easier to create derivatives, which essentially is a package redesign and not a way more costly chip tape-out. Having said that, designing silicon interposers and silicon bridges is still more costly than just an organic package substrate, since effectively they require tape outs too but at much more affordable technology nodes.

Ensuring safe, reliable operation

One major concern on multi-die designs for automotive OEMs is their long-term reliability. Even if each chiplet is designed according to automotive quality and reliability standards, assembling them on a complex package substrate with tens of thousands of micrometer-size connections is still concerning. Recently, multiple initiatives have commenced in the industry to validate quality and reliability of multi-die designs for automotive. The automotive industry is highly regulated, so, as with their monolithic counterparts, multi-die designs must adhere to standards and guidelines to ensure that they’ll operate as intended for the duration of a vehicle’s lifespan. For example:

Open chiplet ecosystem

The idea of an open chiplet ecosystem for automotive designs has been raised more than a few times this year. With such an ecosystem, or marketplace, designers could choose chiplets from the best vendor for a particular function and be able to quickly develop differentiated derivative multi-die designs. Yet, how to address standardization remains the big question, one that reaches across all aspects of the multi-die design and calls for greater collaboration across the automotive ecosystem.

As the industry explores these issues, we might see smaller efforts emerge. Perhaps the initial availability of two chiplets, instead of several, integrated into a package. This smaller-scale approach might lend itself to proof-of-concept testing to address reliability concerns. With sectors such as AI and high-performance computing already embracing multi-die designs, proven design and verification flows, silicon lifecycle management solutions, and die-to-die IP are readily available to facilitate silicon success.

Multi-die designs for automotive will need to support increasingly demanding compute workloads in harsh, often unpredictable environments.

Captive multi-die packages designed and controlled within one company are already a reality today. In the automotive industry, they will likely come toward the end of this decade, due to the increased compute demand of SDVs. But an open chiplet ecosystem is still a vision that will probably take until the next decade to come to fruition.

Christian Malter is Executive Director - Sales Central Europe for Synopsys