Advanced Packaging and Chiplets Under Microscope at DesignConAdvanced Packaging and Chiplets Under Microscope at DesignCon

To learn more about current design and implementation issues with next-generation electronics packaging, check out these technical sessions.

Spencer Chin, Senior Editor

January 13, 2025

3 Min Read
Chiplets and advanced packaging will be examined in several DesignCon sessions.
The implementation and signal integrity issues surrounding chiplets and other advanced packages will be the subject of several DesignCon technical sessions.Intel

Chiplets have generated a lot of interest in recent years as design engineers look for alternatives to traditional system-on-chip technology to house complex, multi-function electronics. At the upcoming DesignCon show from January 28 through 30th at the Santa Clara Convention Center in Santa Clara, Calif., there will be several sessions addressing proposed packaging solutions and the signal integrity issues involved in implementing advanced electronics packaging.

Design engineers whose daily work involves electronics packaging should consider these sessions:

On Wednesday, January 29 at 9 am, a session titled, “Innovative Interposer Solutions for HBM3/4 with CoWoS Technology: A Path to 12.8Gbps,” will address the trend toward high-density packaging solutions for high-density memory. The talk will discuss an efficient SI-PI layout optimization methodology, developed alongside a novel crosstalk shielding structure (patent pending approval) that significantly reduces crosstalk, enables higher speeds for HBM 3 and HBM 4 high-bandwidth memory. It will evaluate chip on wafer on substrate (CoWoS) variants (CoWoS-S/R/L), determining optimal variant, stack-up layers, and routing pattern for HBM3/4-12.8Gbps. 

Later that morning at 11 am, a session titled, “UCIe vs. BoW: Choosing the Right Chiplet Standard,” will describes how the UCIe 2.0 and BoW (Bunch of Wires) standards facilitate better signal integrity in chiplet interconnect, enabling designers to tackle the challenges in complex chiplet systems with intuitive methods. Through real-world application examples, the session will explore the key features of these interconnect standards and their role in supporting the growth of chiplet interconnects. Signal integrity engineers will gain insights into using electronic design automation, s-parameter analysis and eye diagram analysis to characterize their chiplet system, thereby leveraging these technologies to enhance system-level signal integrity.

Related:Chiplets Make Case for More Apps

Addressing chiplet integration, a Wednesday, January 29th  2 pm session titled, “Fast Design & Simulation of Photonics Computing Chip Base on Chiplet-Based Heterogeneous Integration,”  presents the fast design and simulation method of photonics computing chip base on chiplet-based heterogeneous integration. To deliver higher bandwidth and latency, many digital-to-analog converter chips have been placed side-by-side with photonics on silicon interposers. This session’s presenters propose a new method for fast signal integrity analysis and meshed ground parameter optimization, which includes accurate channel model building and fast analysis in both frequency and time domains with IBIS models to enable full signal coverage.

Related:Cheeky Chiplets Meet Super NoCs

At the same time and date, a session titled “Fast BER Analysis Technique for Next Generation Chiplet Simultaneous Bi-Directional Transceiver,” examines the concept of single-ended simultaneous bidirectional (SBD) signaling. This paper proposes a novel statistical modeling methodology based on double-edge response (DER), and captures the generation of echo noise which is the key for SBD signaling modeling. The modeling considers asymmetric rising and falling edges, nonlinear filtering effects, and uncertain phase relationship between the outbound TX signal and near-end inbound received RX signal. The accuracy of the proposed method is validated with spice simulation for a high-speed SBD link.

On Wednesday, January 29 at 3 pm, a session titled, “Deep Reinforcement Learning Based Design Optimization of Power/Ground Ball Map in BGA Package in 3D-ICs Considering Multiple Power Domain Environments,” examines a U-net based deep reinforcement learning (DRL) approach to optimize the power/ground ball map design in 3D-ICs BGA packages, considering multiple power domain (MPD) environments. With the incorporation of MPD in 3D-ICs, the ball grid array (BGA) in the package substrate faces design challenges due to power noise interactions between different domains. The proposed U-net based A2C algorithm helps optimize the power/ground ball map and mitigate Simultaneously Switching Noise (SSN).

Related:Semi Industry Pushing to Mainstream Chiplet Design

 For more information on DesignCon, click here.

About the Author

Spencer Chin

Senior Editor, Design News

Spencer Chin is a Senior Editor for Design News, covering the electronics beat, which includes semiconductors, components, power, embedded systems, artificial intelligence, augmented and virtual reality, and other related subjects. He is always open to ideas for coverage. Spencer has spent many years covering electronics for brands including Electronic Products, Electronic Buyers News, EE Times, Power Electronics, and electronics360. You can reach him at [email protected] or follow him at @spencerchin.

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