Kenneth Larsen, Product Marketing Director, Silicon Realization Group, and Twan Korthorst, Group Director Photonic Solutions, Custom Design and Manufacturing Group, Synopsys

Today, any high-performance computing (HPC) application —tracking climate changes, genome sequencing, or streaming the next live event — presents increasing business challenges in managing associated cost and yield. While what links these applications may seem disparate, their die sizes and demand for low latency and high bandwidth connectivity are growing significantly.

As Moore’s law continues to slow advancements at a less predictable pace, newer design technologies and techniques such as integrated photonics and 3DIC design have become increasingly popular among developers in the semiconductor industry.

While both techniques are not new concepts, their advanced ability to drive higher performances at lower power or reduced cost in the design and manufacturing processes has helped to drive their adoption.

Harnessing the Power of Light: Photonic Applications

Let’s begin with photonics — the study of leveraging the power of light began with the invention of the laser in the 1960s. The phenomenon was created with a unique goal to utilize light to perform the functions that electronics would typically accomplish.

Related:DesignCon Keynote: Silicon Photonics Chips Key for Data Centers

In typical electronic chips, electrons pass through electrical components; however, photonics ICs process and distribute information using photons that pass through optical components like lasers, waveguides, modulators, etc. The field of photonics has become mainstream in chip design for the distinctive properties of light that make it possible to create photonic chips and chiplets to transport information over vast distances. Over the years, researchers found that by manipulating the properties of light, devices and systems can be produced that mimic typical electrical devices like amplifiers, switches, and filters.

By transitioning to photonics, designers can expect orders-of-magnitude improvements in speed and power consumption for data communication or in sensitivity for multiple domains of sensing and imaging.

Today, we see increasing opportunities for photonic applications to integrate into the design and manufacturing processes for systems, devices, and ICs. With the help of photonic integrated circuits (PICs), industries like datacom, telecom, and high-sensing applications such as LiDAR and biosensing are achieving higher performance and resolution at lower power. As more companies continue to invest in new architectures, such as optical computing and photonic quantum computing, the growth in these applications will shape optical transceiver design considerations, with the trend toward near or co-packaged optical I/O chiplets and integrated photonics emerging soon.

Related:IDTechEx Report: 3D Electronics Technology Enables Greater Integration

Designing for Scale

While photonics is promising, the challenge designers must be aware of is scaling. The principles of photonics prefer bends instead of sharp corners, which means that a specific square area that the photonic circuit consumes tends to be much bigger than an electrical IC. Typically, designers know how to fabricate large digital ICs with many transistors by building tolerances and redundancies for the fabrication. However, with photonics, fabrication sensitivity is much bigger than designers are used to. The industry is working hard to provide yielding manufacturing processes and designers with mature process design kits (PDK) incorporating these effects.

As mentioned, photonics is not the only field gaining popularity among chip designers. 3DICs are making waves throughout many key application spaces, including data centers, artificial intelligence (AI), 5G infrastructure, HPC, and more.

From 2DIC to 3DIC Design

Compared to its 2.5D IC counterparts, 3D architectures are the more optimal solution for specific application types. Naturally, 3DICs are more suited to provide scalability and densification through compute-intensive workloads by allowing extreme, heterogeneous, and homogeneous 3D integration — a feature that 2D architectures lack. Mobile applications are now tapping into 3DICs for their demand for greater performance in a highly constrained form factor.

While creating multiple systems-on-chips (SoCs) and stacking them together seems simple, the transition from 2D to 3D IC architectures is not as easy.

In the 2DIC world, designers are familiar with developing SoCs using a set of IC tools, methodologies, and flows. Transitioning to 3DICs, designers are looking for the same set of IC flows and methodologies for their design and validation processes. However, designers must create their 2.5D and 3DIC designs in a highly fragmented environment marked by various point-tool solutions with no way to connect them efficiently. Without choice, designers perform highly manual assessments to determine how to place their IP on each die and where to best place associated micro bumps and through-silicon vias (TSVs) to create the most optimal system-integration architecture. Since 3DIC can scale to hundreds of millions of connections, the lack of integrated analysis and feedback makes this task error-prone, impractical, and inefficient. In a nutshell, to operate increasingly complex designs, jumping from different tools for design implementation, signoff analysis, and design exploration is not a feasible route to expansion.

Another challenge with 3DIC design is the workflow efficiency and efficacy among different teams involved in the design process, such as packaging, IP creation/integration, implementation, design, etc. Typically, in 2DIC, handing over the completed chip-level design to the packaging team would be relatively easy. In contrast, with 3DICs, the resulting design may not meet the performance after packaging, leading to much more back and forth at this stage. This is due to how the system-level optimization happens – it’s up to the chip designer to extract the design’s maximum performance at the architectural level. In a traditional 2D SoC, the level of abstraction has evolved from the transistor to the IP level, while 3DIC abstraction happens at the chiplet level. Given that chiplets can be on different process nodes and support various functions, optimizing the design of chiplets to meet performance targets is much more challenging.

Other foreseeable challenges with 3DIC architecture lie in areas like thermal management and testing. Poor lateral heat distribution and more heat dissipation can result from poor 3D floorplanning, obstructing system performance if not properly managed. On the testing side, a design-for-test approach is needed to identify the trouble spots along the entire stack since testing tools can only access the bottom die. With myriad challenges arising when transitioning from 2D to 3D IC architectures, designers should prioritize smoothing the workflow between different teams to achieve greater productivity and quality of results.

The Next Frontier

The field of photonics and 3DIC are bringing exciting new opportunities in chip design and manufacturing. While working with photonics is demanding, requiring the latest techniques, tools, and research, it is without a doubt that we will see more applications with integrated photonics in the future as engineers learn more about how to best optimize designs to achieve the desired performance.

And while there are challenges that 3DIC engineers will need to overcome, this new technique is still a more optimal solution for designers moving forward than the techniques that came before it, like 2D architectures. From now on, integrated photonics and 3DIC are poised to soon become more widespread among chip designers for their appealing capabilities, thus achieving the highest derivable performance at the lowest power.