While Intel has seen its fortunes decline in its core processor markets,  the company continues to dabble in other technologies, one of them optical communications. The U.S. Defense Advanced Research Projects Agency (DARPA) has selected Intel for Phase 1 of the Space-Based Adaptive Communications Node (Space-BACN) program, which aims to create a low-cost, reconfigurable communications terminal that will translate information between diverse satellite constellations, at the speed of light. 

DARPA envisions a future where tens of thousands of satellites from private sector organizations deliver broadband services from low earth orbit (LEO). The Space-BACN program intends to create an “internet” of satellites, enabling seamless communication between military/government and commercial/civil satellite constellations.

Intel is one of the 10 teams selected for Phase 1 of this program. The other teams selected to work on the reconfigurable optical modem include Arizona State University and II-VI Aerospace and Defense.

Intel will develop its optical modem solution using experts from its field programmable gate array (FPGA) product group, packaging technologists from its Assembly Test Technology Development (ATTD) division and researchers from Intel Labs.

Related:DARPA Secures Chip Future With Tech Past

Based on its leading-edge low-power Intel® Agilex™ FPGA, Intel will also design three new chiplets that will be integrated using Intel’s embedded multi-die interconnect bridge (EMIB) and advanced interface bus (AIB) packaging technologies into a single multi-chip package (MCP) that includes a DSP/FEC chiplet on Intel 3, the most advanced digital node, that enables low-power, high-speed digital signal processing.

There will also be a data converter/TIA/driver chiplet, which provides the best-in-class FinFET RF signal processing for integration of high-speed data converters, TIAs and drivers. There is also a PIC chiplet based on Tower Semiconductor photonic technologies offers low-loss waveguides and options, such as V-groove, enabling automated high-volume fiber coupling integration and assembly.

Intel has commenced Phase 1 of the program where it will design each of the above chiplets and work with the other program participants to fully define the interfaces between the system components in each of the other technical areas. Phase 1 will last 14 months and conclude with a preliminary design review.

At the completion of Phase 1, selected performers in the first two technical areas will participate in an 18-month Phase 2 to develop engineering design units of the optical terminal components, while performers in the third technical area will continue to evolve the schema to function in more challenging and dynamic scenarios.

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Spencer Chin is a Senior Editor for Design News covering the electronics beat. He has many years of experience covering developments in components, semiconductors, subsystems, power, and other facets of electronics from both a business/supply-chain and technology perspective. He can be reached at [email protected].