Low-voltage device dilemma

DN Staff

April 8, 2002

5 Min Read
Low-voltage device dilemma

The Advanced Ultra-low-voltage CMOS (AUC) family gives engineers low-voltage logic in a small, chip-scale package. Low power consumption means less heat to dissipate.

Current trends in advanced digital electronics design continue the push for lower power consumption, lower supply voltages, faster operating speeds, smaller timing budgets, and greater loads. Many designs are making the transition from 2.5 to 1.8V, and bus speeds are increasing beyond 200 MHz.

But for engineers trying to hit all of these targets, the requirement for signal integrity (the fidelity of the transmitted signal as seen at the receiving device) becomes more difficult to achieve. Ideally there should be no overshoots or undershoots (ringing) that impact timing-causing erroneous data, an increase in power consumption, and even damage to the inputs of the receiver.

Why the push? Consumers are demanding greater degrees of portability in PDAs, cellular phones, notebook computers, digital cameras, and MP3 players, to name a few products. But this trend stretches the devices' abilities to meet performance requirements, while at the same time being packaged into smaller and lighter form factors and consuming less power in order to increase battery life. The trends in fixed computing, networking, and telecommunication equipment are similar. Perhaps the best example of this can be seen in the 1U (1.75-inch tall, 19-inch wide, rack-mounted) form-factor packaging of servers that is seeing exponential growth. The challenges of packaging so much computing capability into higher densities include power consumption and heat dissipation.

When going to lower-voltage standards to save power, engineers have to design to tighter voltage margins or guardbands, such as for 1.8V CMOS between the high output and input voltages (V OH and V IH). Problems arise in discerning a signal with a small band if, for instance, noise on the device transmitted output signal (V OH) causes it to dip below the required input signal level (V IH) of the device receiving it.

Benefits. The primary technique to provide lower power consumption with higher signal integrity is to reduce the valid output signal range-the difference between the voltage seen at the output when the device is putting out a "logic high" (binary one) and the voltage seen at the output when the device is putting out a "logic low" (zero). For example, a 1.8V powered device might have an output of 1.7V in the high condition and an output of 0.1V in the low condition, giving a 1.6V signal range. To accomplish this, lower operating voltages are needed compared to 5 or 2.5V devices. In addition to requiring less energy at lower voltages, reduced output signal ranges likewise cut power consumption. And because smaller geometries of the lower-voltage devices provide a smaller input capacitance load at any particular node, the driving device consumes even less power. Reduced physical geometries of circuits also result in smaller chip sizes and circuit packages along with lower costs.

Lower voltage-node operation benefits the design of electronic equipment in many ways. For portable equipment, there is a reduction in the number of battery cells required to supply power, with a corresponding decrease in overall device size, weight, and cost. Lower power consumption also means longer battery life and potentially fewer battery cells may be required. Finally, for a given clock-speed, devices at lower voltages can have slower output edge-rates (dV/dt) resulting in better signal integrity and more reliable functionality. Signals with slower edge-rates contain less harmonic content and therefore result in less ringing.

The problem. As seen by studying the switching levels of 1.8V logic devices (see sidebar figure), the power supply regulation requirements are relatively stringent (the values of valid high and low states are much closer). For example, a driving device putting out 1.35V (the minimum voltage for a logic high under nominal conditions) results in 0.18V of guardband to the input high minimum requirement of 1.17V. This 0.18V band is all that is available to accommodate induced noise and ringing. Any drop in the power-supply voltage of the driving device, or increase in the power supply of the receiving device, will cause a corresponding decrease in the available margin. Thus output/input devices should be supplied from a common power source in order for the switching levels to track with each other to provide adequate noise tolerance. Note that the VOL to VIL margin is also only 0.18V under nominal conditions and similarly subject to power-supply fluctuations.

An answer. A good solution for 1.8V-node requirements provides a convenient means of interfacing with the abundance of electronic devices currently using the 1.8V node. For example, the circuit design of Texas Instruments' new AUC (Advanced Ultra-low-voltage CMOS) family has been optimized for signal integrity and operation at 1.8V, providing low-power operation to increase battery life and to decrease heat-dissipation requirements in high-density fixed applications. Key feature of the AUC family that allows these is the new ULTTL (Ultra Low-voltage Transistor-Transistor Logic) output circuitry, designed for signal integrity into high-speed, point-to-point, transmission-line load conditions and maintaining the quality of signals delivered to the inputs of its loads. Specifically, the design of the AUC output employs three stages that switch in at different times to control the output impedance during the output transition.

For an application report on ULTTL technology, visit www.ti.com


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