In Data Acquisition, Timing Is Everything

If you doubt the usefulness of accurately timed data, recall NASA's second-by-second analysis of sensor failures during the last moments of the space shuttle Columbia. A careful analysis of the times of failures and the sequences of those failures may offer insight into what happened to Columbia in the minutes before it disintegrated.

At a more mundane level, accurate timing of signals from sensors and other signal sources can yield important information about mechanical structures, power plants, mechanisms, and other devices. But without proper timing, tests may take too long to run and signal-analysis systems may acquire measurements at the wrong times.

Here's an example of how poor timing can reduce profits. A battery producer needs to test groups of batteries prior to shipping them. So an engineer builds a test station that uses a digital multimeter (DMM) to measure battery voltage and relays that connect the DMM to each battery, one at a time. A PC controls the relays and obtains data from the DMM after connecting batteries, one by one.

Because relay contacts "bounce" open and closed for several milliseconds when actuated, the software includes time-delay loops. These loops allow extra time for the contacts to settle and remain closed. But a relay may settle faster than the engineer expected, so over a production shift this wasted time can accumulate and back up a fast production line. The result? Lost profits. But what's the alternative?

The proper use of triggers can simplify the battery-test system. In a better test setup, software controls a multiplexer that connects the batteries to a DMM. And the multiplexer triggers the DMM as soon as the selected relay settles. The host PC receives a "done" signal, also called a flag, from the DMM and reads the voltage before it tests the next battery. Instead of the PC wasting time in delay loops, the batteries undergo testing as fast as possible. Granted, this system costs more than several relays, but the increase in production speed should offset additional costs.

Configuring such test systems requires less effort than engineers may think. They can take advantage of boards for the VXI (VME eXtensions for Instrumentation) and PXI (PCI eXtensions for Instrumentation) buses. Both buses add backplane connections for clocks, triggers, and other signals. On the PXI-bus, for example, a reference-clock signal, trigger-bus signals, and a star-trigger signal handle most timing and control tasks. These signals prove particularly valuable in applications such as environmental-test systems, display testers, and communication testers that require very accurate timing of many data-acquisition channels and that operate at high sampling rates.

Me master, you slave

Suppose a test application requires taking simultaneous measurements from four data-acquisition cards at 20K samples/s. (Test software would set each card to operate at that rate.) Designers of a PXI-based system would program one card to act as a master device. It would accept an external trigger from a pushbutton or a limit switch, or from a command in test software and generate a trigger-bus signal. That signal would go in parallel to the other three data-acquisition cards, called slaves.

Although the trigger signal starts all four data-acquisition cards in unison, they then operate autonomously and acquire samples. Slight board-to-board differences in clock frequencies can introduce small uncertainties in the measurement times. Thus the samples will not align perfectly in time. In most cases, these uncertainties amount to only a few nanoseconds.

Due to ambient conditions and the circuits themselves, every clock source produces some jitter-period-to-period variations in clock timing-and drift-small frequency changes over time. These changes can introduce additional measurement errors. So, if engineers plan to acquire signals at very high rates, they must check manufacturers' specifications to ensure these uncertainties don't contribute significant errors to measurements.

Use one clock

To help achieve better sampling, an engineer can use the PXI master card to provide a single, standard clock signal for the three slave cards. Although using a standard clock to control all four data-acquisition cards doesn't do away with jitter and drift, they have the same effect on all four cards.

If a test system requires higher-speed sampling, say above a few Msamples/s, the time delay in the trigger and clock signals on the PXI backplane may introduce small time errors. To further reduce timing errors, engineers can take advantage of a 10-MHz common-reference clock provided on the PXI bus. Equal-length circuit traces for this clock signal keep the signal skew to &1 ns from slot to slot. PXI cards could divide the 10-MHz signal to yield the sample frequency they need. But many card manufacturers supply a phase-lock loop (PLL) that will "lock" to the reference signal and provide proper timing alignment for on-board circuits. (A PLL acts like a closed-loop control that keeps signals in phase.)

When a system requires super-accurate timing, designers can substitute an external oscillator for the common-reference clock. External oven-controlled crystal oscillators, for example, produce a 10 MHz signal with an uncertainty of 1 Hz. Other clock sources, such as a rubidium oscillator can provide even more stable signals, but at significant cost-about $3000 for an add-in PCI-bus card.

High-speed measurements also require a trigger signal that must arrive simultaneously at each card. A card in slot 2 in a PXI system can produce a trigger signal that the backplane distributes to other cards in a "star" topology. Like the common reference clock signal, the star-trigger signal travels to each slot through a separate equal-length signal trace. A star-trigger signal reach the slots with an uncertainly of &1 ns.

Slight timing differences still occur, though. An external trigger signal always triggers the PXI-bus master first. Then circuitry on the master board causes a slight delay before the trigger signal reaches the star-trigger bus. The bus itself causes a slight delay due to the propagation of the trigger signal down the physical conductor. If this slight delay-on the order of a few nanoseconds-causes timing-alignment problems, engineers can bypass the master card and feed the trigger signal directly to all data-acquisition cards.