Avnet's Virtex-6 FPGA DSP Development Kit

DN Staff

February 18, 2010

2 Min Read
Avnet's Virtex-6 FPGA DSP Development Kit

ELECTRONICS: Avnet Inc. announces the availability of the Xilinx® Virtex®-6 FPGA DSP Development Kit as part of the Xilinx Targeted Design Platform for DSP design. Order entry is now open for the $2,995 kit that includes a device-locked version of ISE® Design Suite: System Edition 11.4, which can be downloaded today so developers can quickly get started on their designs.

Wireless, aerospace and defense, instrumentation and medical imaging applications and other computationally intensive applications demand greater digital signal processing performance and functionality to support high-performance systems. This thirst for performance is made all the more challenging when combined with the need to react to emerging and or changing standards. FPGAs provide an ideal solution to these problems; single-chip TeraMAC/s performance and re-programmability that enable differentiation in a changing world.

To address this challenge, Avnet has worked with Xilinx to develop and release the first DSP development kit that combines Virtex-6 FPGA devices, a scalable development board, DSP IP, complete documentation and cables, with a Targeted Reference Design, and the DSP development tools required to evaluate, modify and extend the design. For the first time, DSP designers can compare the merits of RTL against high-level design flows that use languages such as C/C++ and MATLAB® / Simulink®  software to determine the best design flow to bring their products to release. The Virtex-6 FPGA DSP Kit provides up to a 10x productivity advantage and an easier entry point for using FPGAs for DSP. By combining the elements of a total solution, the kit enables users to focus on the unique value of their design from the beginning of their design process.

A key component of the kit is the pre-configured and fully validated Virtex-6 DSP Targeted Reference Design. This design serves as a basis to illustrate DSP techniques and design flows for Virtex-6 class of signal processing functions. The state-of-the-art digital up converter (DUC)/digital down converter (DDC) Targeted Reference Design shows customers how to use advanced techniques such as clock over sampling, time division multiplexing and using high-performance DSP48 slices for optimizing signal processing performance and resource use. The design flow based on Simulink and MATLAB from The MathWorks allows algorithm developers to create DSP hardware designs using a familiar modeling environment without the need to learn RTL. Experienced RTL designers are provided design techniques for creating efficient DSP hardware using ISE Design Suite and LogicCore DSP IP along with verification methodologies for comparing functional correctness against high-level algorithm models.

Below are the key deliverables of the Virtex-6 DSP Targeted Reference Design:

  • Design Source files for RTL and Simulink

  • Top level system integration RTL source files

  • Simulation environment

  • Test benches

  • Implementation environment

  • Complete steps and parameters for design synthesis

  • MAP, place and route and timing closure

  • Targeted reference design tutorials including recommended flows for design modification and integration

-Edited by Kelsey Anderson

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