Topology Affects Common-Mode Current Flow Paths

April 4, 2005

8 Min Read
Topology Affects Common-Mode Current Flow Paths

It is well known that electronic systems—products and devices—circulate currents in two modes: single-ended, and differential. These two modes of current include all signals and power distributions. Differential mode currents are generally balanced with respect to some common reference such as a center-tap between the differential pair, or a common image (so-called "ground") return. What is less understood is that single-ended signals and power are actually differential as well! The "differential" characteristic is found in between the "high" signal and "the return"!

When another unintended current becomes superimposed into the process of intended signals or power currents, a form of "series modulation" will result. This "modulation" couples a percentage of the unintended current into the desired signals or power processes. A disruption of the operational functionality of the circuits may result. How does this happen, and through what mechanisms?

Mechanical Features

As peculiar as this might sound, many of these mechanisms relate to mechanical features in design. In order to examine these processes, it is useful to visualize interactions between mechanical features with electrical results.

Consider the mechanical visualization of what happens when current at radio frequencies (or transients) is conducted on to a plane.

The figure at the top describes the pattern of magnetic flux that will result.

Now we look at what happens when mechanical apertures are introduced into the pattern of current. What we see is that the flux becomes redistributed to produce circulating currents around the apertures.

The middle figure shows us a redistribution of flux, and that a sequential cascade of common-mode Field potentials, EcmA …C will result across the apertures.

Fact of physics: When apertures are mechanically close together compared to the size of the apertures, something known as an "array effect" is produced. This effect means that each of the field potentials developed across each aperture will accumulate or "sum up" in combination. The mechanical analogy is that a bunch of springs are stacked together. More springs, more bounce.

The figure at the bottom describes that the net effect of the "array" of field potentials, as losses in the plane, will be dramatically affected by electrical inductance.

As applied to electronic products, where does one find such an aperture array effect? Why, in most circuit boards, of course!

The figure 2A (right) visualizes that "array effects" are formed by "holes" (apertures) drilled into the planes of circuit boards. The result is that two "common-mode" loss regions are noted. Ecm1 is what I call "patterned layout inductance" since the "vias" that are around each circuit device cause this in board layout. The second, Ecm2, is a region within the packaging of the circuit device itself.

In most circuit boards these effects are inevitable, although "blind and buried" vias that are not drilled through all planes will mitigate the conditions. Production costs for "blind via" boards, however, are often prohibitive for high-production commercial products.

So what happens? The expansion of the effects are shown at right.

The figure at left (2B) views a cross-section of the equivalent electrical process. The common mode current, ICM flows across the "holes" causing losses across the equivalent inductance L2 and the field potentials ECM1, which couple to signals, Is. The inductance L1 in the circuit package receives a part of this energy in power and signals, and sets up ECM2. Another field ECM3 can be then setup between the circuit device and the planes of the board. This can also be seen as Ediff, a differential superimposed into the Is signal current as a consequence of ICM shown as a transient or "glitch" as the excitation source.

In terms of mechanical analogies to electrical effects, it is like the circuit device is a trampoline bouncing due to the hole surrounding it!

So, what can be done?

Essentially, the most effective method is simply to inspect the mechanical decisions for the "layout architecture and topology" of any product design. Then, visualize how mechanical layout decisions, particularly in regard to locations of interface (including power) cables, will impact the common-mode intrusions into circuits. The goal: "Direct" all possible common-mode currents into regions of least circuit intrusion! If the common-mode offending current isn't there, the circuit cannot be perturbed for operational functionality!

The majority of common-mode currents that can cause operational and reliability issues in functionality tend to come from "outside" the product. That means the locations of cables become significant considerations. With the general understanding of how common-coupling occurs in circuit boards as illustrated by the prior descriptions, it can be seen that mechanical locations of cables that can convey offensive currents can be the first line of defense!

The figure at the top of the next page illustrates an example of how to essentially guarantee that there will be common-mode issues in any circuit board.

The two wires/cables have been located on opposing sides of the board. A common-mode current, ICM, is accordingly "forced" across all three integrated circuit devices including all apertures that are located around each device.

Essentially, this "architectural layout error" will tend to assure that a sequence of field potential losses will be experienced within the circuit board. These are shown as the series E1 through E6, respectively forming across the patterned layout inductance (L1–L5) surrounding each device, IC1 through IC3. In this cross section, essentially all signals and devices are at risk for functional issues due to common-mode superimposition effects/coupling. This is due only to the choice of cable or wire locations.

In contrast to this example, the alternative would be to locate cables or wires to a "region" where the common-mode current can locally circulate and not "flow through" vulnerable circuit-layout regions.

The figure 3A (right) describes that with the cables co-located in close mutual positions, any common-mode current flow will be confined to a small region between the cables. This method "protects" the circuit regions from common-mode noise intrusion.

When paralleled circuit boards are required, the mechanical locations of interface become even more critical to assure control of common-mode effects. When not appropriately considered, essentially all of the circuit and signal topologies could suffer operational intrusions due to common-mode currents.

Figure 4A (below) diagrams that common-mode architectural current flows will dramatically impact multi-board products if the mechanical locations are not planned efficiently. In particular, the current will set up internally radiated fields between the boards, and will dynamically stress the signals in the inter-board connector, shown as E7. In this example, there is simply no region of the layout that is "safe" from common-mode intrusion effects.

The solution to implementation of paralleled boards can be relatively simple if mechanical locations are chosen to avoid common-mode intrusions.

Figure 4B (above) provides an example where mechanical mounting and connector positions interact to improve the effectiveness of common-mode controls. The result will be that the product will have increased immunity to noise intrusions.

Here, the cable connector that was located on the top board has been relocated to the lower board. A new, interface-transition connector has been added between the boards. This connector transfers the functions for the cable that are on the top board, and brings them to the lower board. The transition connector, if equipped with multiple ground connections, will "null" field potentials between the two boards. This null position is considered to be "N5". The other nulls, which are ground-to-ground shorts through mechanical devices (such as stand-offs), are also provided to control any common-mode currents related to chassis, and these are shown as N1 through N3. The position at N4 assured that any losses across the inter-board connector are minimized. Result: Any offensive common-mode currents are controlled and directed into a small region, interface to interface, avoiding any significantly possible intrusion into the circuit regions.

So what is the process? Consider each connection to either import or export intrusion currents. Set up an "architectural plan" so that these currents do not invade sensitive circuit regions.

Web Resources

Another way of examining the detail of the common-mode noise process is to consider equivalent effects in the arrangement of the signals (or power) "transmission lines." The tech-stuff for those who wish to explore this topic further can be found at

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