Single-, Multi-Phase Buck RegulationSingle-, Multi-Phase Buck Regulation

This article examines the synchronous buck regulator topology, both single- and multi-phase variants, apropos its widespread implementation and popularity in systems requiring step-down dc-dc voltage conversion, such as point-of-load (POL), automotive and voltage regulator module (VRM) converters. The application space runs the gamut from lower current highly integrated monolithic regulators in single- and multi-cell lithium ion battery portable applications to low voltage, very high-current multi-processor server supplies. The recent popularity, perceived advantages and abundant methods of multi-loop current-mode control (CMC) as applied to buck regulator output voltage regulation have shifted focus away from single-loop voltage mode control (VMC) as the loop control methodology of choice. This may have emanated from the conventional wisdom that when compensating voltage mode converters, more design choices are necessary and significant a priori knowledge and experience are required to extract a successful design. This myth will be debunked via an intuitive and unified explanation of single- and multi-phase buck converters and their control using VMC. Control loop compensation is analyzed using a unified small-signal model. Finally, a straightforward control loop design procedure is described.

Single-Phase Buck Converter Topology

The power stage schematic diagram of a typical dc-dc buck converter cell with output voltage Vo and output current Io is illustrated in Figure 1, above. Ideal components are shown and parasitics such as switch on-state resistance, inductor dc resistance (DCR), capacitor equivalent series resistance (ESR) and equivalent series inductance (ESL) not represented. The high side switch, SH, is driven by a PWM signal for time ton in each switching period of duration Ts. The duty cycle ratio D is given by:

The low side switch, SL, is driven complementarily with duty cycle (1–D). Both switches operate at fixed switching frequency ƒs = 1/Ts. The output filter consists of inductor Lƒ and capacitor Cout. The input filter capacitance is denoted by Cin. The input and output capacitor currents are iCin(t) and iCout(t), respectively, with polarity as indicated. Typical current waveforms for the buck topology operating in continuous conduction mode (CCM) are also indicated in Figure 1. In synchronous applications, switches SH and SL are implemented with n-channel high side and low side MOSFETs.

Multi-Phase Buck Converter Topology

An interleaved multi-phase buck converter[1] power train with N phases is typified in Figure 2, below. Essentially, two or more identical, interleaved buck converter circuits are connected so that their output is a summation of the outputs of the individual phases. The multi-phase circuit has manifold advantages[1] over its single-phase cousin. The captioned current waveforms in Figure 2 are based on three interleaved phases (N = 3) operating in CCM. The high side and low side switches are denoted by S1H, S2H,…, SNH and S1L, S2L,…, SNL, respectively. Usually, the switches are implemented using n-channel high side and low side MOSFETs to maximize conversion efficiency. The gate drive timing is designed such that the phase shift between adjacent phases is 360°/N.

The duty cycle ratio D is as before, given by equation (1). Ideally, the phase inductors have equal inductance, Lf1=Lf2=…=LfN=Lf and current sharing amongst phases is exact. Thus, the dc and ac components of phase inductor currents are presumed equal. The duty cycles and output currents of each stage are equal as given by (2), where ILfn refers to the dc level of inductor current of the nth phase.

Unified VMC Buck Converter Small-Signal Analysis

The generalized schematic of a single-channel buck converter using voltage mode control and a type III PID compensation circuit is embodied in Figure 3, below.

A conventional op-amp type error amplifier is shown. The divided down output voltage at the error amplifier inverting input, usually termed the feedback (FB) node, is compared to a fixed reference voltage VREF and a compensated error signal is generated at the compensation node, labeled COMP. This error signal is compared to a saw-tooth ramp voltage at the pulse width modulator (PWM) comparator to generate a duty cycle command for the power stage. Trailing-edge modulation is described herein whereby a turn-on command is activated at the clock edge whereas a turn-off command is imposed when COMP intersects the ramp voltage. Alternative PWM strategies described in the literature include leading-edge and double-edge modulation.

In the multi-phase interleaved buck converter, the duty cycle perturbations at each switch node can be considered the same as there is only one error signal derived from the compensator and one duty cycle command. Thus, these perturbations can be connected together which places the inductors for each phase effectively in parallel. As a consequence, the small-signal model of a multi-phase interleaved buck can be simplified to that of a single-phase buck with the inductance equal to 1/N times the inductance of each phase, specifically Leq=Lf/N. Essentially, the multi-phase small-signal model can be reduced to that of the single-phase circuit by appropriate scaling of the phase inductance. The analysis can proceed based on a single-phase equivalent circuit. The appropriate small-signal average model[2] for both the single and multi-phase circuits is given in Figure 4, below. By perturbation and linearization around a dc operating point, the small-signal duty cycle perturbation, designated d(t), actualizes a resultant variation in output voltage, vout(t). For simplicity, the block diagram does not show the elements to represent ac input variation, vin(t), or load current variation, Îload(t), since the subsequent analysis will set these variations to zero.

The open loop control-to-output voltage transfer function in the Laplace domain is given by equation (3), or more succinctly in its normalized form by

ð˜LC and ð˜ESR represent the LC filter complex double pole and output capacitor ESR zero, respectively. CO is the output capacitance value appropriately derated for applied voltage and operating temperature, RL is the effective load resistance and RDAMP is the effective damping resistance associated with the inductor and power FETs. The PWM modulator gain is inversely proportional to the peak-to-peak ramp voltage, or

The compensator transfer function from output voltage to COMP is given by equation (4) or more succinctly by

The type III compensator produces three poles and two zeros. One pole is located at the origin for high dc gain while the other singularities, indicated in Figure 3, are determined by component values as follows

The open loop gain T(s) of the system (as measured by breaking the loop, injecting an oscillator signal and analyzing the frequency response using a gain-phase analyzer) is given by

VMC Buck Converter Compensation Design

The conventional compensation strategy[3] employed with type III voltage mode control is as follows:

Finally, a resistor divider network from VOUT to FB determines the desired output voltage. Note that the lower feedback resistor, RFB2, has no impact on the control loop from an ac standpoint since the FB node is the input to an error amplifier and effectively at ac ground. Hence, the control loop can be designed irrespective of output voltage level. The only caveat here is the necessary derating of the output capacitance with applied voltage.

The crossover frequency, fc=ð˜c/2ð±, where the loop gain is 0dB, is usually selected within 1/10 to 1/5 of the switching frequency. By considering the loop gain transfer function close to crossover and realizing that ð˜p1 cancels ð˜ESR and ð˜p2 is located well above crossover, we obtain the expression as follows

Routinely, RC2 && RFB1, particularly with ceramic output capacitors when the ESR zero is located at high frequency. Substituting s = jð˜c into (12), a simple solution for the crossover frequency with type III voltage mode control is derived as

Knowing the desired location of the compensator poles and zeros, values for RC2, CC1, CC2 and RFB1 can be calculated, assuming an initial value is selected for RC1. RFB2 is then selected based on the desired output voltage.

Figure 5, right, top, shows a bode plot of the loop gain and phase of a typical system. The poles and zeros of the system are marked with x and o symbols respectively, and a + symbol indicates the bandwidth at crossover. The phase margin, ð§M, is the difference between the loop phase and –180 degrees. A target of 45 to 60 degrees for this parameter is usually ideal. More phase margin can be dialed in by locating the compensator zeros at a frequency lower than the LC double pole. Figure 6, right, middle, and Figure 7, right, bottom, typify the individual gain and phase plots of the LC filter, modulator and compensator.

Note the loop crossover frequency increases with input voltage since the loop gain is proportional to input voltage. As a consequence, it is recommended to design the compensation at maximum expected VIN. Some voltage mode PWM controllers[4] advantageously include an input voltage feed-forward feature where the ramp amplitude is increased proportional to input voltage, thus substantially eliminating loop bandwidth variation and significantly improving line transient performance.

About the Author:

Timothy Hegarty is staff applications engineer, Infrastructure Products Group, National Semiconductor, Tucson, AZ.