MEMS Resonator Takes on Quartz Crystals

DN Staff

July 17, 2006

2 Min Read
MEMS Resonator Takes on Quartz Crystals

Replacing well-established technology is always a tricky proposition. Researchers have been trying to displace quartz crystals with Micro-Electromechanical system (MEMS) resonators for more than 40 years. Based on a new wafer encapsulation approach, SiTime Corp. may finally have a viable solution. The company's MEMS-First wafer-level encapsulation and packaging technology addresses the stability and low cost required for high-frequency oscillator applications.

Built in epitaxially sealed epipoly (epitaxially grown polysilicon) chambers buried under the wafer surface, the MEMS resonator structure is isolated from external contamination prior to packaging. A vacuum of approximately 10 mT seals out water and other high- vapor pressure contaminants at the wafer level. After dicing, the resonators are molded into standard plastic IC packages.

Testing showed a total frequency error of less than 100 ppb under a measurement noise floor of 200 ppb and a specified measurement error of 30 ppb. Measurements were made of the compensated frequency stability for the resonator in a plastic molded package as it was swept twice from 40 to +85C and back to 40C. The hysteresis was less than about 50 ppb. Over a one year timeframe, the MEMS resonator drifts less than 1ppm compared to typical small quartz crystals that drift 3- to 5ppm.
Specified in the frequency range of 1- to 125 MHz, initial production fixed frequency and programmable oscillators have a frequency tolerance of plus or minus 50 to plus or minus 100 ppm and aging of plus or minus 2ppm/year. The units are specified at plus or minus 150 psec of peak to peak jitter. Four-pin QFN type packaging options for the MEMS resonators include: 2.0 x 2.5 x 0.85 mm, 2.5 x 3.2 x 0.85 mm, 3.2 x 5.0 x 0.85 mm, and 5.0 x 7.0 x 0.85 mm packages.
For more information on SiTime oscillators, go to

INTEGRATED STRUCTURE Fabricating the MEMS mechanical resonator in a standard CMOS process allows the integration of additional circuitry on the surface to provide further system cost reduction and improved performance.

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