The PCIe, or Peripheral Component Interconnect Express standard, has been around for nearly 20 years. It was an upgrade to the earlier PCI bus, developed by Intel and introduced in 1992. The bus provided a 32-bit parallel interface, although the standard allowed for 64-bit architectures.
Today, the PCIe is a high-speed serial communications bus, more like a network-on-a-board than the old-style parallel interface of PCI. As a modern serial bus, the PCIe standard can implement SerDes, which refers to Serializes and Deserializes digital data used in high-speed chip-to-chip communication. Modern SoCs for high-performance computing (HPC), artificial intelligence (AI), automotive, mobile, and Internet-of-Things (IoT) applications implement SerDes via PCI Express (PCIe), MIPI, Ethernet, USB, and other standards.
One of the latest applications for PCIe is in the data center. As demand for ultra-low-latency and AI and machine learning (ML) applications increases, data centers are being forced to add servers to meet peak demand. However, servers are generally sized the same in terms of computing, memory, and networking capacity ratios. But surprisingly, the average compute-intensive workload doesn’t always use all the available memory. Such ineffective use of memory resources is why some data centers opt for the increased use of virtual servers.
Using PCIe in the data room has gained much more interest thanks to the adoption of the new Compute Express Link or CXL, open standard interconnection for high-speed processor-to-device and processor-to-memory applications. CXL builds upon the PCI Express (PCIe) technology by adopting the PCIe 5.0 PHY as its physical interface. With next-generation server platforms providing PCIe 5.0 Generation support, there will be a growing ecosystem of PCIe 5.0 devices being offered in the marketplace.
Many component vendors are now offering enhanced devices to enable the continuing migration of PCIe into the data room. To be successful, these components must support server-based processors, i.e., to meet the Intel CK440Q specification and future Intel Xeon processor requirements.
An important component in any PCIe design is the clock generator. Recently, Renesas introduced a new low-jitter clock generator IC designed specifically for the next generation of high-performance computing and data centers. The company’s 9SQ440 device is an Intel CK4440Q server-compliant clock generator that addresses PCIe Gen5 design challenges.
PCIe clock generators are the heart of PCIe timing and with tighter specification requirements for the latest standard. The better PCIe Gen5-compliant clock generators provide significant design flexibility and margin for customers. These devices can serve as a centralized clock generator for server CPU and PCIe clocks. The ICs also support differential outputs as well as jitter performance – less than 50fs RMS of PCIe Gen5 common clock phase jitter – to meet the timing requirements for topologies ranging from simple, single-board 2-socket to complex, modular multi-socket systems.
Regardless of the generation of the PCIe bus, the clock remains the most basic hardware component. The clock generator produces the timing signal that controls the data rate of the bus. Traditionally, a clock buffer is used to control the rise and fall time of the clock edges. Maintaining the cleanest clock rise and fall time is made difficult by the presence of jitter, which causes the clock edge to degrade from its ideal location and shape. Clock jitter is typically caused by the generator circuitry, thermal noise, power supply variations, and interference coupled from nearby circuits.
As the data speeds increase with each generation of PCIe bus, so does the potential for jitter. Yet, the actual jitter specification for the clock is constantly lowered to meet speed and timing issues. For reference, the PCIe Gen4 jitter limit is 500 femtoseconds (fs) rms, whereas the Gen3 limit was 1picoseconds (ps) rms. The jitter budget for the reference clock in a PCIe Gen5 system is 250fs max.
Thus, the clock generator is the most crucial element in maintaining the proper PCIe system performance and reliability.
John Blyler is a Design News senior editor, covering the electronics and advanced manufacturing spaces. With a BS in Engineering Physics and an MS in Electrical Engineering, he has years of hardware-software-network systems experience as an editor and engineer within the advanced manufacturing, IoT and semiconductor industries. John has co-authored books related to system engineering and electronics for IEEE, Wiley, and Elsevier.