Upgrade Your Engineering Know-How at DesignCon

With electronics applications becoming more varied and complex with packaging densities and signal speeds growing ever higher, design engineers face ever-greater challenges in the development of next-generation electronics. This year’s DesignCon Show in Santa Clara, California from January 28 through 30^th will help design engineers tackle those mounting challenges by highlighting the latest electronics advances and design know-how in a rich variety of exhibits, technical sessions, and networking opportunities.

While the exhibits and majority of technical sessions will occur January 29^th and 30^th, there’s no reason not to attend the information-rich tutorials and sessions on Tuesday, January 28^th. On that day, DesignCon attendees can further upskill through a wide range of courses teaching some of the latest design methodologies and exploring some of the current most pressing challenges in electronics design. Below, we have listed several interesting tutorials that are worth attending, as well as some early panel sessions where industry experts will discuss what’s new and important in selected areas.

Check the DesignCon site for detailed information and course and session times.

What’s new in high-speed verification

Given the ever-higher speeds engineers must design and test for, this tutorial titled“Design & Verification for High-Speed I/Os at 10 to 112, 224 Gbps & Beyond with Jitter, Signal Integrity & Power Optimized” should not be missed. It reviews the latest design and verification developments, as well as architecture, circuit, and deep submicron process (14, 10, 7, 5, 3, 2 nm) technology advancements for high-speed links, with an emphasis on jitter, noise, signal integrity, and FEC for 10 – 128,224 Gbps, and beyond high-speed I/Os (e.g., GbE (10G, 40G, 100G, 200G, 400G, 800G, 1.6 T, 3.2T), CEI/OIF (11G, 18-28G, 36-58G, 72-116G, and 144-232G, and beyond), Fibre Channel (16G, 32G, 64G, 112G, 224G), and PCI Express (8G,16G, 32G, 64G, 128G).

Related:DesignCon 2025: The Place Engineering Speakers Meet

Open standards UEC and UALink designed for AI/ML with lower power and latency, will be reviewed and discussed. Example studies on design and validation methods will be presented.

Examining crosstalk 

Crosstalk is a common issue in PCB and packaging interconnects due to their open waveguiding nature. The interconnects tend to leak signal energy and are exposed to interference from neighboring links and from distant links via PDN structures. The effect on signal is getting worse with the increase of data rates. Understanding how crosstalk occurs, how to model and evaluate it, and how to reduce it are key. This tutorial titled “How Interconnects Work: Crosstalk Anatomy & Quantification” addresses these questions. Different types of crosstalk are illustrated and explained with power flow density visuals from 3D EM analysis. The course also compares various methods for both quantifying and mitigating crosstalk.

Related:Key Takeaways from DesignCon 2024

The latest in PCI and PAM4

Titled “PCI Express & PAM4: Balancing Silicon & Interconnect Interdependencies for 128 GT/s,” this panel will focus on the latest updates and changes to PCIe signaling and physical topologies, focusing on the PAM4 signaling in the PCIe 7.0 specification. PCI Express technological advances to 128 GT/s enables system designers to achieve much needed and desired improvements in data throughput aiding advances in the deployment of artificial intelligence inference engines and co-processors topologies in the data center. Considering the 128 GT/s targeted data rate, the course will discuss the pathway to manage the system needs for this new specification revision. There are numerous challenges at the silicon chip level, chip packaging, and system board level requiring new techniques in simulation and post silicon validation. Building upon this panel’s past contributions, this year's participants bring a diverse knowledge base to discuss the latest advancements simulation, design, and innovative test and measurement methodologies required for these current and future PAM4 inflection points. 

Related:Vote for the DesignCon 2025 Engineer of the Year

How do you power AI?

ICs for AI are increasing the power requirements exponentially. This requires innovation in delivering power while architecting chips to keep power need manageable. This panel, titled “Powering the AI Semiconductor Stack: Power Strategies for High-Performance AI Computing,” will discuss the rapid increase in power needed to drive the latest AI chips and how to address those.  It will discuss how high power requirements are expected to go and if the increase can be supported.  This panel will plan for discussion between IC customers and power infrastructure suppliers. 

Don’t forget pc board laminates

While many of today’s electronics design issues revolve around signals and circuits, the choice of printed board laminates, long an issue, becomes even more critical given today’s complex multi-layer boards. This tutorial titled, “Stackups: The Design Within the Design,” will guide design teams through the process of evaluating and selecting the right set of laminates and trace routing strategies to create PCB stackups that meet the requirements of complex, multilayer boards. This allows designers to create boards that work right the first time, within budget, and with reproducible results across multiple fabricators.  This year’s tutorial will build on material from previous years, including a deeper dive into factors that impact Dk, Df, impedance and loss, along with material anisotropy and copper roughness. It will also explore design decisions that impact fabrication costs, including HDI.