Micron Ups the Ante On DRAM Technology

New 1-beta process improves memory density and power efficiency to benefit mobile, AI apps.

Spencer Chin, Senior Editor

November 1, 2022

3 Min Read
Micron will incorporate its power-saving 1-beta process technology on its double data rate 5X (LPDDR5X) mobile memory.Image courtesy of Micron

Although the memory market has hit some rough patches amidst falling PC demand, memory suppliers continue to make strides advancing memory technology. This time, it is Micron Technology’s turn. The Boise, Idaho-based memory supplier has debuted its next generation of DRAM process technology, called 1β (1-beta), and begun shipping qualification samples to select smartphone manufacturers and chipset partners.

Micron has debuted 1β on its low-power double data rate 5X (LPDDR5X) mobile memory, delivering top speed grades of 8.5 gigabits (Gb) per second. Micron stated the node delivers significant gains across performance, bit density, capacity and power efficiency, all of which will benefit end memory markets. Micron believes 1β will find applications beyond mobile, in low-latency, low-power, high-performance DRAM for uses ranging from intelligent vehicles to data centers.

The introduction of 1β is Micron’s latest move to cement its position in the highly competitive memory market, which is expected to experience robust long-term growth as data needs explode, noted Thy Tran, Vice President of DRAM Process Integration for Micron, in a press briefing earlier this week. She expects memory consumption to grow to 221 zetabytes by 2025 (it was 81 zetabytes in 2021), where 1 zetabyte is the equivalent of 1 trillion gigabytes, with key driving factors the growth of artificial intelligence and machine learning and autonomous vehicles.

Related:Micron Targets Autonomous Vehicles With ASIL-certified Memory

Micron began volume shipments of memory made through its 1α (1-alpha) process node in 2021, and this past July Micron’s also began shipping of the world’s first 232-layer NAND.

The new 1β node is expected to deliver around a 15% power efficiency improvement and more than a 35% bit density improvement with a 16Gb per die capacity. As Micron’s LPDDR5X memory will be the first to incorporate the process node, mobile applications will be the first to benefit from the memory’s density and performance advantages.

“The 1β technology is very important for mobile phones,” said Ross Dermott, Vice President of Mobile Product Line Management for Micro, during the press briefing. “There is a need for high storage in mobile phone cameras.  1β technology provides a lower power footprint and enables more phone apps to run concurrently.”

The power savings are also enabled by the implementation of new JEDEC-enhanced dynamic voltage and frequency scaling extensions core (eDVFSC) techniques on this 1β-based LPDDR5X. The addition of eDVFSC at a doubled frequency tier of up to 3,200 megabits per second provides improved power savings controls to enable more efficient use of power-based off unique end user patterns.

Related:Electronics Suppliers Forging Ahead on Capex Investments

Lithography, nanomanufacturing advances

To achieve higher memory capacity in a smaller footprint, Micron employed leading-edge nanomanufacturing and lithography methods, including proprietary, advanced multi-patterning techniques and immersion capabilities to more precisely pattern miniscule features. The higher density will enable smartphones and IoT devices to fit more memory into compact footprints.

The advances were in part made possible through company investments in process technology and manufacturing infrastructure, with Micron fabs transformed into highly automated, sustainable and AI-driven facilities.

Although Micron has announced plans to expand its manufacturing footprint in the U.S., the 1-beta DRAM will be manufactured in Micron’s existing plant in Hiroshima, Japan.

Over the next year, the company will begin to ramp the rest of its portfolio on 1β across embedded, data center, client, consumer, industrial and automotive segments, including graphics memory, high-bandwidth memory and more.

Spencer Chin is a Senior Editor for Design News covering the electronics beat. He has many years of experience covering developments in components, semiconductors, subsystems, power, and other facets of electronics from both a business/supply-chain and technology perspective. He can be reached at [email protected].

About the Author(s)

Spencer Chin

Senior Editor, Design News

Spencer Chin is a Senior Editor for Design News, covering the electronics beat, which includes semiconductors, components, power, embedded systems, artificial intelligence, augmented and virtual reality, and other related subjects. He is always open to ideas for coverage. Spencer has spent many years covering electronics for brands including Electronic Products, Electronic Buyers News, EE Times, Power Electronics, and electronics360. You can reach him at [email protected] or follow him at @spencerchin.

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