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DARPA Secures Chip Future With Tech Past

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With the SAHARA project, DARPA will secure future chip designs by moving from FPGAs to structured ASICs.

The ongoing chip shortage is a real problem. Solving it a tactical issue, one that requires carefully planned, incremental steps in the short term to solve a nearer-term problem. But making sure the U.S. can securely design and manufacture the semiconductor chips needed for defense is a strategic, long-term concern. This is where the Defense Advanced Research Projects Agency or DARPA comes in.

Recently, DARPA announced the “Structured Array Hardware for Automatically Realized Applications (SAHARA) program, which aims to expand access to domestic manufacturing capabilities to tackle challenges hampering the secure development of custom chips for defense systems.”

Leveraging the design and manufacturing expertise of Intel and select university partners, SAHARA’s goal is to enable the automated and scalable defense-relevant field-programmable gate array (FPGA) designs into quantifiably secure Structured ASICs. The program will also explore novel chip protections to support the manufacturing of silicon in zero-trust environments.

There is a lot of information packed into this statement. To help break it down into accurate and understandable pieces, Design News talked with Serge Leef, Program Manager for the Microsystems Technology Office (MTO) at DARPA. 

Design News: What’s really going on with this announcement?

Serge Leef: There is a convergence of interests here. Intel acquired a structured ASIC company called eASIC several years ago. Since then, multiple factors aligned to make a compelling case for possible collaboration.

Design News: I remember that structured ASICs were big news in the 2003- and 2004-time frame. They were heralded as the bridge between programmable FPGAs and typical ASICs – i.e., non-programmable standard-cell-based ASICs. FPGAs were highly customizable but tended to be slower, more power-hungry, and expensive than ASIC chips, which were intended for high volume, standardized functionality, and low power.

Serge Leef: Back in that timeframe several major ASIC companies tried to enter the Structured ASIC business, but numerous technical and economic factors ultimately drove them away.  Since then, the technology and business models have become more favorable and drove a renewed interest in Structured ASICs, but until Intel’s acquisition of eASIC there were no suppliers in this space with sufficient critical mass to work with the DoD (Department of Defense). Still, the considerable investment will be needed to truly make the eASIC platform secure enough for defense and other applications.

The DoD has many FPGA designs that would benefit from a transition into a structured ASIC, which cost an order of magnitude less than standard ASICs to design and manufacture.

Design News: Aren’t structured ASICs similar to gate array technology from the 1980s? Gate arrays contained unconnected logic gates that could be configured after the fact – by adding a couple of metal layers – to implement a custom logic function. Gate arrays had much lower NRE than full custom ASIC chips because only a couple of metal layers worth of masks were required.

Serge Leef: Structured ASICs are customized with two or three layers that are derived from the user's design. Now, Intel’s architecture is not exactly like a gate array, but the principle is similar.

But unlike FPGAs – which is why they appeal to DoD designers - structured ASICs (and ASICs) have the disadvantage that they can reveal the design information to a manufacturer, opening the door for possible cloning, counterfeiting, and reverse engineering. The reason that FPGAs are more secure is that they contain no design information while being manufactured. The design information gets inserted into an FPGA after the chip has been delivered.

Design News: So how do you make sure that the design of the customizable layer in a structured ASIC is sufficiently secure and cannot be reverse-engineered at a random third-party fab?

Serge Leef: That's the crux of SAHARA. We want to create something as close as possible to a push-button process where you take RTL (the actual design information) that was originally destined for FPGA implementation and turn it into a structured ASIC. Right now, it's a lengthy and manual process.

The second goal of SAHARA is to add security mechanisms into the design that enable manufacturing in the zero-trust environments

Design News: By zero-trust environment, do you mean a foreign fab where you have no certainty about the security of the fab?

Serge Leef: Yes – to make it secure enough that it can be manufactured anywhere in the world because it has no design information that can be compromised.

Design News: Wouldn’t a fab located within the U.S. be secure, like Intel?

Serge Leef: While Intel is a domestic fab, it is not certified as a “trusted foundry”. I’m not commenting on the relative security of our domestic fabs. I simply mean that they haven’t gone through the certification process which can be lengthy, expensive, and not particularly lucrative. It may not be in the best economic interests of a fab to do so.

Design News: One last question – Does DARPA’s plan to expand domestic manufacturing of custom DoD chips by changing FPGA designs to structured ASICs have anything to do with the current shortage of semiconductor chips in the U.S.?

Serge Leef: The current shortage of chips is an immediate term tactical issue for certain segments and the US economy that is now receiving significant attention from the Government. DARPA’s focus, however, is on the strategic solutions, typically on a five-to-ten-year time horizon.

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DARPA’s Structured Array Hardware for Automatically Realized Applications (SAHARA) program.

John Blyler is a Design News senior editor, covering the electronics and advanced manufacturing spaces. With a BS in Engineering Physics and an MS in Electrical Engineering, he has years of hardware-software-network systems experience as an editor and engineer within the advanced manufacturing, IoT and semiconductor industries. John has co-authored books related to system engineering and electronics for IEEE, Wiley, and Elsevier.

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