Timing relationships between signals are critical to reliable operation of digital designs. With synchronous designs, the timing of the clock signal relative to data signals is especially important. Tracking down setup and hold violations can be tedious work, but mixed signal oscilloscopes offer digital channels for testing many data lines at once, and often have triggering capabilities that can help speed up the process. In this article we offer tips and tricks that will make performing this task easier using a mixed signal oscilloscope (MSO) with automated setup and hold triggering capability.

Setup time is defined as the time the input data signals are stable (either high or low) before the active clock edge occurs. Hold time is the time the input data signals are stable (either high or low) after the active clock edge occurs. As shown in Figure 1, violations occur when these conditions are not met. Setup and hold times are specified in component data sheets for synchronous devices (such as flip-flops) and must be met to assure that the component will behave correctly and reliably.

An MSO is an effective tool for identifying setup and hold violations because it can capture both analog and digital representations of signals and display them in a time-correlated format. These instruments combine the analog signal capture capabilities of an oscilloscope with the basic functions of a logic analyzer.

The timing resolution of an MSO is important to note, since this will determine your ability to measure timing differences. Timing resolution can vary considerably for mid-range MSOs typically used for these applications, ranging from about 2 ns for more affordable units down to 0.2 ns for higher-end MSOs with higher sample rates.

Setting Digital Thresholds

A mixed signal oscilloscope’s digital channels view a digital signal as either a logic high or logic low, just like a digital circuit views the signal. This means as long as ringing, overshoot, and ground bounce do not cause logic transitions, these analog characteristics are not of concern to the MSO. Just like a logic analyzer, an MSO uses a user-specified threshold voltage to determine if the signal is logic high or logic low.

The MSO’s analog channel can be used to check the logic swing of a digital signal. As shown in Figure 2, the MSO in this case automatically measures the digital signal amplitude as about 3.6 V. For logic families with symmetrical voltage swings like CMOS, the threshold is at half of the signal amplitude. However, for logic families with asymmetrical voltage swings like TTL (Transistor-Transistor Logic), you typically need to consult the component data sheet and define the threshold as half-way (TTL Vthreshold = 1.4V) between the logic device’s maximum low-level input voltage (TTL VIL = 0.8V) and minimum high-level input voltage (TTL VIH = 2.0V) values.

Some MSOs provide per-channel threshold settings that can be used for debugging circuits with mixed logic families, as shown by the example in Figure 3. In this case, the TTL signal threshold was set to 1.7 V, the 3.3 V CMOS signal thresholds were set to 1.65V, and the 5 V CMOS signal thresholds were set to 2.5 V. This enabled reliable acquisition of the various logic signals at the same time.

Color Coding and Grouping Speed Analysis

Digital timing waveforms look very similar to analog waveforms except only logic highs and lows are shown. To make analysis easier, some MSOs show logic lows and logic highs in different colors on the digital waveforms, allowing you to see the logic value even if a transition is not visible. The waveform label color also matches the probe color-coding to make it easier to see which signal corresponds to which test point, as shown in Figure 4.

For additional analysis the digital timing waveforms can be grouped to create a bus. One digital signal is defined as the least significant bit and the other digital signals represent the other bits of the binary value up to the most significant bit. The MSO then decodes the bus into a binary or hex value.

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Remove Timing Skew

To simplify digital measurements, modern MSOs compensate for the propagation delay of logic probes. Therefore, there are no digital channel probe deskew adjustments. However, for better time-correlation measurements between the analog and digital waveforms, it’s important to remove the analog to digital time skew.

In the example shown in Figure 5, to align the analog channels with the digital channels, the 2 V (50% amplitude) position on the analog waveform was time-aligned with the digital signal transitions which occurred at the 2 V threshold. The deskew value was manually adjusted to align the analog channel to the digital channel. This deskew process needs to be repeated for any other analog channels.

Analog channel skews should be checked when the analog probes are changed and the digital thresholds should be checked when measuring a different logic family. With the threshold and skews configured, the MSO is ready for verifying and debugging digital circuits.

Flip-Flop Measurement Examples

Many memory and communications interfaces specify critical setup and hold times, but the simplest synchronous logic device is a flip-flop. In a D-type flip-flip the logic state of the D Input appears at the Q output only after the rising clock edge (after a propagation delay). In this example, we used a 74HCT74 dual positive-edge triggered, D-type flip-flop.

Initially, the device looked like it was working as expected. The data signal had been stable for several nanoseconds before the rising edge of the clock, and the data remained stable for many nanoseconds after the clock edge. The propagation from clock edge to the Q output was about 6 ns. But as we discovered, as shown in Figure 6, in one instance the data signal transitioned just 300 ps before the clock edge, well below the 15 ns setup time specification – a setup time violation. Notice that the Q output did not change state as expected. The gray regions around the signal transitions indicate the timing uncertainty related to the digital sample rate.

Similarly, Figure 7 shows an instance where the data signal is transitioning about 300 ps after the clock edge. This is well below the 3 ns hold time specification for the device– a hold time violation. Again, notice that the Q output does not change state as expected.

Capturing Setup and Hold Violations

Many MSOs have a specialized trigger mode designed to automatically capture every setup and/or hold violation. The setup and hold trigger measures the timing relationship between the clock and data signal and captures signals when the setup time or hold time is below the specification. Some MSOs can measure the timing between a clock and multiple data lines at once. This capability simplifies debug, but also can be used for unattended monitoring of a design.

To use this function, first refer to the component data sheet for setup and hold trigger parameters, which can then be set on the scope to capture any violations. Once configured, the MSO will automatically trigger on the first input condition that violates the specified parameters.

To show how setup and hold triggers work, let’s take a look at a 74LVC1G74 D-type flip flop. After consulting the 74LVCG74 component data sheet, we set the setup and hold trigger parameters (2 ns and 1 ns, respectively) to capture any violations, as shown in Figure 8. In this case, the MSO triggered on a hold violation where the data changed inside the specified 1.12 ns hold time..

By adding logic analyzer functionality to an oscilloscope, MSOs facilitate fast digital debugging. As shown in the previous examples, MSOs make it quick and easy to identify and measure setup and hold violations in digital designs.

[All images courtesy Dave Pereles / Tektronix]

Dave Pereles, a technical marketing manager at Tektronix, has worked in the test and measurement industry in various roles including applications engineering and product management for over 25 years. He holds a BS in electrical engineering from Trinity College, Hartford, Conn., and an MBA from Seattle University.