As the name suggests, signal integrity deals with the integrity of an electrical signal. It all stems from the fact that digital signals are not really binary values of “1” or “0” but are analog voltage (or current) waveforms. As such, these waveforms are subject to the real-world, physical effects of noise, distortion, and loss. If the distances are short and at low bit rates, then a simple conductor will transmit a waveform with acceptable fidelity. However, at high bit rates and over greater distances or through different mediums, then several effects can degrade the electrical signal to the point where errors occur, data is compromised, and devices fail.
In practice, signal integrity consists of a set of measurements that determine the quality of a signal as a way to analyze and mitigate the effects of noise, distortion and loss. It is a set of design practices and test that address how the electrical properties of almost any interconnect cab mess-up the (relatively) pristine signals that come from integrated circuit chip and how these problems can be fixed. There are two common signal integrity electrical design concerns, namely, the timing and the quality of the signal. Does the signal reach its destination when it is supposed to? Is it in good condition when it gets there?
Electronic and electrical packages are full of interconnects that can affect signal integrity within a chip and throughout a printed circuit board (PCB). For example, consider the changes that a signal may experience when traveling through even a short connector. If there are instantaneous impedance changes, then some of the signal will reflect and the rest will probably have some distortion. In simple terms, there may be ringing in the circuit, often due to multiple reflections between impedance discontinuities at various interface ends.
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Before you can solve a signal integrity problem you must first understand its root causes. One of those causes is the timing of high-speed systems, which depends on the delay resulting from the physical length that the signal must propagate. It also depends on the integrity of the shape of the waveform when it reaches the other end of an interface. Signal waveform distortions can be caused by different mechanisms, but common causes include:
- Reflection Noise: This is due to impedance mismatch, stubs, vias and other interconnect discontinuities.
- Crosstalk Noise: Here, the problem arises from electromagnetic (EM) coupling between signal traces and vias.
- Power - Ground Noise: Parasitics of the power and ground conductors and fast simultaneous switching of various output signals are the cause for this problem. It is sometimes called Ground Bounce, Delta-I Noise or Simultaneous Switching Noise (SSN).
One modern source of signal integrity headaches comes from the common Serializer/Deserializer (SerDes) connections that are used in high speed communications. SerDes blocks are used to convert data between serial data and parallel interfaces in each direction, typically to compensate for limited input and output. Maintaining SerDes signal integrity has become increasingly difficult as data rates increase from 28Gbps to 56Gbps and even higher.
|Image Source: Grégoire Surrel, CC BY-SA 4.0|
Signal integrity has become a critical part of the chip and board design process. In the past, all that was needed to deal with SI problems was to carefully model and test passive interconnects of resistors, capacitors, inductors and the like. Now, the entire SI link must be modeled, including the transmitter, receiver, clock and channel. The results of such modeling, sometimes called link analysis, will directly affect the selection of design architecture, including equalization, clocking, timing calibration, as well as coding and/or error correction.
The approach for modeling SI starts with the prediction of SI perform, followed by creating and equivalent circuit model for all components and links and finally, simulating the performance of components, links, critical nets and the whole system.
The better that performance can be predicted, the easier it will be to find and fix problems early in the design cycle, thus reducing development and production costs.
In addition to modeling and simulation, test equipment is needed like logic analyzers and mixed signal oscilloscopes. Perhaps the most common test associated with signal integrity is the generation of an eye diagram on an oscilloscope. Viewing eye diagrams can help with finding crosstalk, electromagnetic interference (EMI), signal loss and other phenomena that affect signal integrity. The term “eye” refers to the fact that the pattern on the oscilloscope looks like an eye.
To learn more about the different types of instruments used in signal integrity applications, be sure to attend the signal integrity tutorial at Design2020. To see all of the signal integrity events, click here.
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A few years back, Heidi Barnes of Keysight Technologies and DesignCon 2017 Engineer of the Year, notes that improvements in signal integrity will be needed to improve cloud communications, greater availability of digital information, and more energy-efficient server farms.
“It all has to do with speed,” she told Design News. “The amount of digital information that people want to consume and use in the cloud and in the IoT – all of it demands signal and power integrity.”
The integrity of the power network through a chip or board started to become a concern well after the challenges from signal integrity were well understood. Now, the power supplied to digital circuits has become of great concerning, requiring designers perform a power integrity analysis.
Some feel that power integrity analysis is more complex than basic signal integrity because the former deals with energy and it distribution through the chip or board. In other word, power integrity is concerned with energy moving in the x and y directions, as opposed to just back and forth on a transmission line or board trace.
Regardless, the goal of both power and signal integrity is similar, namely, to determine the impedance of in the conductance path. In signal integrity, we are trying to match the impedance of a trace to a certain value, often 50 Ω. Power integrity want the power domain network to have the lowest impedance possible. For AC circuits, this means minimizing the impedance between the power and the ground.
The right impedance and other transmission line characteristics are critical for both signal and power integrity. Both these topics and much more will be covered in detail at DesignCon 2020.
|Image Source: DesignCon 2020|
January 28-30: North America's largest chip, board, and systems event, DesignCon, returns to Silicon Valley for its 25th year! The premier educational conference and technology exhibition, this three-day event brings together the brightest minds across the high-speed communications and semiconductor industries, who are looking to engineer the technology of tomorrow. DesignCon is your rocket to the future. Ready to come aboard?
John Blyler is a Design News senior editor, covering the electronics and advanced manufacturing spaces. With a BS in Engineering Physics and an MS in Electrical Engineering, he has years of hardware-software-network systems experience as an editor and engineer within the advanced manufacturing, IoT and semiconductor industries. John has co-authored books related to system engineering and electronics for IEEE, Wiley, and Elsevier.