STEM efforts are sprouting up everywhere to encourage engineering as a career and prepare them for a lifetime of learning. At this year’s DesignCon in Santa Clara, a new program called 40 Under 40 is providing an opportunity for up-and-coming engineers to further their careers through full free access to the show’s full conference education program, which encompasses 14 tracks plus DesignCon’s growing automotive-focused Drive World conference.

Under the program, engineers nominated themselves or a fellow engineer under 40 years old as of February 2, 2024, through an online portal. All applications were reviewed and 40 applicants from across the globe, from different companies and organizations, and various focuses were accepted.

The 40 engineers selected receive a complimentary Education pass to DesignCon 2024, which includes access to all conference and theater sessions at the event and the expo, Welcome Reception, and Booth Bar Crawls. The winners also gain access to an exclusive networking breakfast with leading engineers and mentors on Thursday, February 1, 2024, at the show.

The mentors, which represent a who’s who of industry experts in various technical areas, include:

“For nearly three decades, DesignCon has offered an annual gathering for engineers to expand and share their knowledge,” said Suzanne Deffree, Group Event Director, DesignCon. “We’ve seen great minds and influential careers develop among our long-time attendees. With the new 40 Under 40 program, DesignCon takes a firm step forward in ensuring the next generation of engineering leaders have a place to grow their education and innovations at an annual space to connect with peers.”

The 40 Under 40 Program is supported by DesignCon partners Amphenol, Design News, UCSC Silicon Valley Extension, and the College of Engineering & Applied Sciences, University of Colorado Boulder.

The list of 40 under 40 follows below. You can also click here.

Olarn Bampenchow, R&D Test Engineer, Broadcom

Montserrat Benito, Application Engineer, Marvell Technology

Quresh Bohra, Analog Engineer, Intel 

Robert Branson, Signal Integrity Engineer, Samtec

John Chaka, Senior Applications Engineer, Siemens

Sriganesh Chandrasekaran, Staff R&D IC Design Engineer, Broadcom

Tushar Chauhan, Package Design Engineer, Senior Staff, Marvell Technology

Bichen Chen, Hardware Engineer, Apple

Yuan Chen, Sr. Electrical Engineer, Microsoft

Asmita Dani, RFIC Design Engineer, Sonera Magnetics

Benjamin Dannan, Chief Technologist, Signal Edge Solutions

Michael Derrenbacher, Design Verification Engineer, Texas Instruments

Sukanta Dey, Senior EDA Tools Software Engineer, Intel 

Josh Diedrich, Software Design Engineer, Tektronix

Qian Ding, Packaging R&D Engineer, Intel

Yuandong Guo, SI Engineer, Cruise

Yifan Huang, Sr. Signal and Power Integrity Manager, AMD

Licheng (Joshua), Hardware Systems Engineer, NXP Semiconductors

Bonnie Lam, Sr. Electrical Engineer, Microsoft

Chaofeng Li, PhD Student, EMC Lab, Missouri University of Science and Technology

Jun Liao, Principle Engineer, Intel

Sinan Liu, Signal & Power Integrity Engineer, Meta

Wei Liu, Signal & Power Integrity Engineer, Intel

Abishek Manian, Analog Design Manager & Senior Member of Technical Staff, Texas Instruments

Shubhankar Marathe, Sr. ESD System Design Engineer, Amazon Lab126

Christian Naumann, Signal Integrity Engineer/ Power Engineer, Cisco Systems

Scotty Neally, PMTS Analog Design Engineer, AMD

Deepak Pai, RF Desense Engineer, Meta Platforms

Justin Patterson, DSP Software Engineer, Tektronix

Guilherme Paulino, System Engineer, Lumentum

Kyle Sammon, Staff System Architect, TE Connectivity

Greylan Smoak, Signal Integrity Engineer, Samtec

Tim Wang, Signal Integrity Application Scientist, Keysight Technologies

Tao Wang, Sr. EMC Engineer, Amazon

Scott Witcher, Signal/Power Integrity Engineer, Chipletz

Yang Xu, EMC Engineer, Cruise

Ming Yang, Systems Engineer, Alphawave SEMI/University of Toronto

Guanshun Yu, Staff ASIC Design Engineer, Qualcomm