Lately, news about the free and open RISC-V Instruction Set Architecture (ISA) has been garnishing a lot of attention. One reason is that RISC-V might become a less expensive yet viable competitor to the global processor leader Arm, especially if the latter is acquired by GPU-giant Nvidia.
Even before the potential announcement of Arm by Nvidia, the RISC-V platform had gained a large following among system-on-chip (SoC) designers, thanks in part to its standardized development platform and diverse ecosystem.
RISC-V is a processing architecture, but not a processor implementation. This removes the bias toward a particular microarchitecture or silicon technology. RISC-V is a free, open-source ISA that is based on reduced instruction set computer (RISC) principles. That’s why it’s hardware processor agnostic. RISC-V can be implemented in an ASIC or FPGA, and on any process node.
Thus, rather than paying for a proprietary ISA, e.g., from Arm or Intel to accompany their respective processors, a developer can use the open-source RISC-V ISA as a basis to create their own processor implementations. These implementations can be used for in-house development, to sell as commercial off-the-shelf (COTS) physical devices, or even license them as intellectual property (IP) cores that can be used in other chip designs.
One example of the latter is SiFive, a fabless semiconductor company that produces both licensable IP cores and customizable silicon based on the RISC-V ISA. Also, SiFive provides a RISC-V–based, Arduino-compatible board called the HiFive1. Many other companies supply RISC-V IP cores including Andes Technology, Codasip, Bluespec, and Cortus, among others.
Several companies provide RISC-V soft-core implementations targeted for FPGAS, such as Microsemi, Rumble Development, and ORCA. RISC-V based platforms are even appearing on the edge. GreenWaves Technologies offers a battery-powered, AI-enabled and RISC-V supported IoT device.
RISC-V Based Toolchains
There are several major open-source, compiler framework projects that provide many of the tools needed for the RISC-V toolchain. One is the GCC (GNU Compiler Collection) project, which is an open-source initiative providing compiler support for many of the RISC-V standard ISA variants. GCC also offers support for both Linux and “Bare-metal” (RTOS and no operating system) targets.
Another provider is the LLVM project, a newer open-source compiler framework initiative that also provides compiler backend and library support for RISC-V standard ISA variants. While the LLVM project has traditionally focused on Linux OS target operating system support, there is growing interest within the community to extend support for embedded bare-metal target devices.
Eclipse is a commonly used open-source-based, integrated development environment (IDE) for software development. Eclipse can be used to develop almost any kind of software but is often used for Java applications. It is the front-end compilers offered by Eclipse that matter the most as it relates to RISC-V. Several vendors, such as Microsemi, offer free development environments that are Eclipse-based.
|Language Support||C, C++|
|Host OS Support||Windows, Linus|
|Target OS Support||Bare-metal (RTOS or no OS)|
|Target Hardware Support||SiFive, Ibex, others|
Perhaps one of the biggest listings for tools is provided on RISCV.org. This list contains simulators, debuggers, C compilers and libraries, boot loaders and monitors, kernels and operating systems (OS), and integrated development environments (IDEs).
In addition to open-source tool suites, a large ecosystem has evolved to support RISC-V development. For example, the RISC-V Foundation now boasts more than 200 member companies. Also, there are numerous developers of RISC-V implementations and RISC-V tools around the world.
Adding processors to FPGA fabrics is nothing new. One of the most compelling reasons is that FPGAs offer designers the choice of sequential logic - as used by most processors - or parallel logic FPGA architectures. Traditional processors execute familiar sequential processing programs. Conversely, programmable fabrics like FPGAs can implement just about any hardware function needed to augment the sequential processing capability.
“Programmable fabric is inherently parallel by nature since multiple hardware blocks can operate simultaneously, either in parallel where logic is duplicated or in a pipelined fashion,” explains Tim Morin, Technical Fellow, Microchip Technology, Inc. “The open ISA of RISC-V-based processors grants users the freedom to innovate in ways that they couldn’t before, e.g., by choosing an off-the-shelf CPU IP from existing vendors.”
Adobe Stock, FPGA
|Multi-core RISC-V SoC can be implemented in ASICs and FPGAs.|
John Blyler is a Design News senior editor, covering the electronics and advanced manufacturing spaces. With a BS in Engineering Physics and an MS in Electrical Engineering, he has years of hardware-software-network systems experience as an editor and engineer within the advanced manufacturing, IoT and semiconductor industries. John has co-authored books related to system engineering and electronics for IEEE, Wiley, and Elsevier.