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September 14 – Day 4 – Synthesis and Layout

CEC Semester Twelve 2017
September 14, 2017 - 2:00pm EDT

Once a design has been developed in a HDL and tested and verified, we need to lay it out on the chip.  This is analogous to layout for ASICS but it is not as complicated since we are using an existing regular structure.  Layout is important because of the effect on performance and the interaction of multiple algorithms that might be implemented together.  Layout tools generally give the engineer a high level of control while allowing for modes that let software pick.  We look at these options and approaches.

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