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September 13 – Day 3 – HDL

CEC Semester Twelve 2017
September 13, 2017 - 2:00pm EDT

Algorithms for FPGAs are specified via a Hardware Description Language (HDL).  We will look at a couple of these, VHDL and Verilog.  Many design tool sets support both.  The one you use will depend on standards and skills available in your shop.  We will also look at some of the tools used to convert these HDLs to RTL form.

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