If you missed DesignCon, you missed a lot. Below you can sample a small handful of the more than 80 technical papers presented at DesignCon 2018 by engineering experts in the fields of test and measurement, power integrity, and signal integrity.
Click through and gain knowledge on interconnect systems, eye diagrams, high speed serial data signals, DC-DC converters, DDR5, and more.
Mark your calendar now for DesignCon 2019, Jan. 29-31!
Applying IBIS-AMI Techniques to DDR5 Analysis
DDR5 memory is slated to run at speeds from 3200 MT/s to 6400 MT/s. These speeds are well into the range where Tx/Rx equalization is used to ensure reliable signal transmission in serial channel applications. DDR5 is expected to make use of the same techniques (FIR, CTLE, DFE) to improve signal quality when the final DDR5 specification is published.
While DDR5 signaling speeds have reached traditional SerDes speeds, there are significant differences between DDR and serial channel applications, including:
• Shorter lower loss channels with more discontinuities and reflections
• Multiple driver / receiver combinations
• Multiple signal terminations
• Single-ended signaling
• Variable network topologies (DIMMs present or absent)
• Short transmission bursts followed by network I/O reconfiguration
• Bi-directional signaling
At first, application of SerDes equalization techniques and AMI models seems like an obvious approach to improving DDR5 signal quality. A closer inspection reveals that the design problems incurred by DDR5 topologies are quite different than the signaling challenges that SerDes equalization techniques were originally designed to overcome. However, thoughtful application of AMI models and AMI simulation techniques can highlight which DDR5 signal quality issues are significant and what techniques can best be used to overcome them.
This paper looks at the challenges of achieving reliable data transmission for a DDR5 data net operating at a variety of speeds. We discuss how AMI-style analysis can be used to identify which data transfers are the limiting factors in high speed performance and what equalization / modeling techniques can be used to address them.
Elastomeric-based Interconnects Use Waveguide Structures to Enable Terabit Networks by Minimizing Physical Layer Pathologies
In this paper, the authors present a novel interconnect system for the internet infrastructure of network and data centers. This interconnect consists of a full differential system including twinax cables that are directly attached to conventionally fabricated printed circuit board using a technology that can eliminate the connector. This topology can significantly reduce loss and impedance mismatches within the entire transmission system. The interconnect structure consists of an interposer directly inserted into the board. The interposer comes in two different topologies: H-pin and conductive elastomer. Both configurations allow for a high degree of flexibility when designing the high-speed system. Such flexibility allows for a wide array of PCB materials to be used to optimize the cost/performance ratio.
The Gap Between Eye "Mask" Compliance, BER and BER Contours
Various methodologies existed over recent decades for treatment of eye diagrams. These coexist and in some ways, collide. One such example is “mask compliance”. From the 1950s through the early 1980s, mask testing consisted of a grease-pencil shape drawn on the reticule of an analog oscilloscope … and instructions to be sure the oscilloscope trace stayed inside or outside of the shape.
With the advent of digital oscilloscopes, methods appeared that approximated this kind of test in a more precise fashion. The grease pencil was abandoned. The mask was more precisely specified and drawn. The matter of detecting and recording a mask violation became more objective.
Fast-forward 20-25 years and we have notions of Bit Error Ratio (BER) and contours of constant BER based on statistical analysis of digitized waveforms and eye diagrams. Mask tests are still around … but few seem to know precisely what they mean; just that they seem prudent. Here, we examine the meaning of Eye diagram mask testing, BER contours, BER and the relationships between them.
Improving TDECQ and SNDR for Better Characterization of Serial Data Signals, and Path from Mask Test to TDEC, SNDR, and TDECQ Measurements
The test of high speed serial data signals has developed from mask test to TDEC, transmitter and dispersion eye closure. With signaling moving to PAM4, measurements move in two directions: SNDR for PAM4– signal to noise and distortion ratio, a transmitter test tool which sums noise and other non-compensable features into one figure-of-merit number; and the TDECQ, transmitter and dispersion eye closure penalty quaternary. We summarize these developments, and in an original work we show improvements for SNDR and TDECQ for the near future.
Measuring Current and Current Sharing of DC-DC Converters
The measurement of current in power converters, especially in switching DC-DC converters, is a very important task. This paper will establish a practical range for the time constants that we need to cover and will illustrate the effectiveness of DSP-based corrections for a few selected time-constant values. It will be shown and illustrated that even though the voltage across the capacitor of the RC element rides on the ‘quiet’ output voltage, for multiple reasons the common-mode voltage range and common-mode rejection of the measurement circuit is still very important. This paper analyzes the noise floor, dynamic range, confidence level and measurement speed of the impedance measurement solution.
Examining System Challenges When Implementing Next Generation Data Center Input/Output (I/O) Connectivity
As the networking industry moves to develop higher data rates to support next generation demands, there are also simultaneous demands to support higher Input/Output (I/O) port densities, higher I/O module power dissipation, improved signal integrity, maintain cable reach and satisfactory electromagnetic interference (EMI) performance. In this paper, we will discuss the comparative differences of three state-of-the-art port types including micro quad small form-factor pluggable (microQSFP), quad small form-factor pluggable double density (QSFP-DD) and octal small form-factor pluggable (OSFP). These new I/O ports address the conflicting performance demands in different ways and the comparative performance differences will be presented using a combination of simulation and measurement methods. A summary will be provided highlighting the relative ability of the different port types to meet next generation market needs.
112G Electrical System Performance Study Based on an Improved Salz SNR Methodology
In early system design stage for 112G when no silicon nor hardware components are available, an improved Salz SNR analytical model is derived and a methodology for assessing system margin is introduced. Unlike traditional ICR based Salz method, major noise terms that are recognized to be dominant and are weighted much higher in PAM4 than in NRZ systems are included. Performance ‘upper limits’ such as maximal tolerable insertion loss and crosstalk for ‘optimal’ modulation scheme is analyzed based on six backplane link architectures and those with higher possibility to meet the ‘upper limits’ are selected based on full channel modeling for margin analysis.
16Gb/s and Beyond with Single-Ended I/O in High-Performance Graphics Memory
GDDR5 has emerged as a leading DRAM interface for applications requiring high system bandwidth like graphic cards, game consoles and high-performance compute systems. However, the requirements of newer applications drive even higher memory bandwidth. The paper discusses the development of GDDR6 as a lower-risk and more cost-effective solution as compared to other high-bandwidth memory solutions. We further introduce GDDR6 as offering a 2x increase in per-pin bandwidth over GDDR5, while maintaining compatibility with the established GDDR5 ecosystem. Circuit and channel performance scaling will be discussed and validated through measurement to demonstrate the potential for scaling GDDR6 to 16Gb/s.