What Should We Do With the Inputs to Unused Logic Gates & Functions? (Part 1)

I fear the topic of this column is poised to unleash a tsunami of controversy. My engineering accomplice Joe Farr says that this is one of those topics that, when presented to 10 different engineers, will result in a minimum of 15 different opinions. I’m not going to argue. We shall see what we shall see.

Ground rules

Let’s start by setting some ground rules (no pun intended). For the purposes of this column, I’m going to assume we’re working with the 7400-series TTL and 4000-series CMOS devices of my youth. Also, that we are working with trusty digital logic devices (as opposed to their wibbly-wobbly analog cousins). Also, that we are working with logic 0 and logic 1 values of 0 V and 5 V, respectively. Having said all this, the underlying concepts presented here are also relevant to today’s technologies.

This all stemmed from Part 6 in my Ode to Bodacious Breadboards series of columns. As part of an ongoing clock project, I implemented a 2:4 decoder using two integrated circuits (ICs): a 74LS04 (hex inverter) and 74LS08 (quad 2-input AND). Since my circuit didn’t require all six of the NOT gates presented in the 74LS04 package, the question arose as to what should be done with the unused gates.

For reasons that will become apparent in the discussions below, my knee-jerk reaction was to use pull-up resistors to connect the unused inputs to the +5 V rail. After a little cogitation and rumination, however, I realized there was much more to this than first meets the eye. In fact, I kept on coming up with more and more “what if” use cases.

Related:Ode to Bodacious Breadboards, Part 6

This is one of those topics to which I don’t recall ever seeing a definitive set of rules gathered in one place, so I’m hoping this two-part mega-mini-series of columns will go some way to filling the void.

Unused single-input gates

Let’s start with unused single-input gates, such as NOT (inverter) and BUF (buffer) functions. Without specifying a particular implementation technology at this stage, let’s assume we have six NOT gates in a single 14-pin dual in-line (DIL) package as illustrated below. Let’s further assume that we wish to use the three gates highlighted in green, while the three gates highlighted in purple are to remain unused.

The first option is to do nothing with unused gates.  CLIVE “MAX” MAXFIELD

So, what are we going to do with the unused gates? Our first option, as reflected in the image above, is to do nothing at all. It must be acknowledged that doing nothing at all is one of the things I do best, but that’s not an optimal solution in this case.

As a rule of thumb, it’s not a good idea to leave the inputs to unused gates floating in this way. In the case of this example, depending on the IC’s implementation technology, there’s a possibility the NOT gates could start to oscillate. Apart from anything else, this will burn power and generate noise in the form of electromagnetic interference (EMI).

Related:Ode to Bodacious Breadboards, Part 1

So, what are our other options? Well, off the tops of our heads, Joe and I came up with six possibilities as illustrated below. The first option (a) is to use a separate pull-up resistor for each unused input (higher cost). A related option (b) is to share a single pull-up between all the unused inputs (lower cost, but potentially more complicated routing, especially if the unused gates are distributed across both sides of the IC). And there’s always the possibility of option (c), which involves connecting the unused inputs directly to the 5V power rail/plane (much lower cost—only slightly higher than doing nothing at all—but undesirable for a variety of reasons that depend on the underlying IC technology).

To pull, or not to pull, that is the question.  CLIVE “MAX” MAXFIELD

Alternatively, option (d) involves a separate pull-down resistor for each unused input; option (e) is to share a single pull-down between all the unused inputs; and option (f) involves connecting the unused inputs directly to the 0 V ground rail/plane.

Related:Ode to Bodacious Breadboards, Part 2

Whatever solution we eventually choose for these inverting NOT gates, we would use the same technique for non-inverting BUF gates, since a BUF is essentially two NOTs connected in series.

Up, down, value?

As fate would have it, I was discussing this topic with Godfrey Manning (amateur radio callsign G4GLM), who is based in Greater London. Godfrey made mention of the fact that regular TTL inputs are floating emitters (multiple emitters on the same transistor where a gate has more than one input). Unconnected, they are functionally logic high, although they won't read as such when using a logic probe.

This means that, in the case of our example above, it’s best to connect an unused input to +5 V via a pull-up resistor. This is because the gate will consume a tiny bit less power than if we used a pull-down resistor to connect the input to ground. Of course, the amount of power being saved will be miniscule, but—all other things being equal and any other considerations notwithstanding—it’s better to save power than to not save power (call me “old fashioned,” if you will).

By comparison, in the case of CMOS logic gates, which are implemented using PMOS and NMOS transistors connected in a complementary fashion (see my book Bebop to the Boolean Boogie for more details), it doesn’t matter whether we use pull-ups or pull-downs, just so long as we use one or the other. Having said this, remember that we are still talking about single-input NOT and BUF gates; things will become interesting when we start to consider multi-input gates like ANDs, ORs, etc.

A useful high-level summary of the logic families and their unconnected input options is as follows:

Remembering that, although eagles may soar, weasels rarely get sucked into jet engines, I’m obliged to add the following “weasel words,” which are as follows: “Always consult the data sheets for the specific components you are using” (so nothing you do is my fault).

Next time

In the next installment of this two-part mega-mini-series, we will proceed to consider multi-input gates like ANDs, ORs, etc. Also, we will discuss what to do with unused inputs on partially used logic gates and on higher-complexity logic functions. Until that frabjous day, do you have any thoughts on this topic that you’d care to share? If so, please feel free to email me at [email protected].

Please click here for What Should We Do With the Inputs to Unused Logic Gates & Functions? (Part 2).