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High-Speed Interconnects Present Design Challenges
At DesignCon, several discussions examine cabling and signal and power issues implementing high-speed interconnects.
3 Min Read
High-speed interconnect applications that involve protocols such as PAM4 require extra attention to requirements such as power and signal integrity. Samtec
With the clean transmission of high-speed signals a key priority in today’s electronic products and systems, design engineers continue to face the task of designing and implementing interconnection systems that ensure power and signal integrity. At the upcoming DesignCon show January 28 through 30th, several presentations and panel discussions will drill down to the nuances of designing and implementing high-speed interconnects.
All the sessions take place in the Santa Clara Convention Center in Santa Clara, Calif. For more information on DesignCon, go here.
PCI and PAM4
A familiar to topic at DesignCon, PAM4 signaling in the PCIe 7.0 specification will once again take center stage in a panel discussion Tuesday, January 28 at 4:45 pm titled, “PCI Express & PAM4: Balancing Silicon & I nterconnect Interdependencies for 128 GT/s.” Featuring speakers from BitifEye, Keysight Technologies, Amphenol, Samtec, Synopsys, and Intel, the panelists will discuss the pathway to manage the system needs for this new PCIe 7.0 specification revision. They will examine challenges at the silicon chip level, chip packaging, and system board level. Additional topics include correlation between simulation and validation, design practices for PCIe over optical cables and through electrical pathways, and signal integrity complications.
Interconnects for AI
The rapid emergence of AI and machine learning is driving large-volume deployments of 112Gb/s and 224Gb/s interconnects for Artificial Intelligence across the industry. In a session titled “The Path to 448G Interconnect” occurring Wednesday, January 29th at 12:15 pm, a presentation by two speakers from Amphenol will highlight the solution landscape and challenges associated with 224 Gb/s interconnects and look ahead to what’s in store for 448Gb/s and they key milestones along the way.
Can Optical Interconnects Make It?
Engineers have for years looked at optical interconnects as a potential high-performance alternative to copper. On Wednesday at 3 pm, a session titled, “Exploring CopprLink & the Future Towards Electro-Optical Interconnects for Evolving Rack Architectures in Data Centers” will look at the recent PCI-SIG 6.0 and 7.0 performance targets to help evaluate the types of cabling solutions that can be used, along with when and how the transition to optical solutions is likely to occur.
Are Co-Packaged Connectors for Real?
Another promising interconnect technology is co-packaged connectors and cables. In a session titled “Direct to Substrate 200G-PAM4 Co-Packaged Connectors: Is it a Reality?” that takes place Thursday, January 30th at 8 am, several speakers will examine issues such as assembly and process. Enablers for direct to substrate connectivity will be reviewed including package stiffeners, separable interface, ball-less solder, and aggressive miniaturization. Results include on-package reflow trials and VNA and BER measurements comparing full channels with and without CPC.
Cabling for PCIe 7.0
The challenges of internal cabling to meet PCIe 7.0 will be examined in a session titled, “Path to PCIe Gen 7.0: Challenges & Design Considerations for Next Generation Internal Cabling,” taking place Thursday, January 30th at 11:15 am. The paper delves into design improvements at an interconnect level for a near-chip application, signal integrity challenges from PAM4 modulation, ground resonances, and mechanical attributes and reliability. It identifies current generation challenges in signal integrity and proposes design considerations to resolve them to achieve next-generation requirements. A comparative simulation-based performance analysis will be presented between current and next-generation internal cabling.
High-density Cabling
Later Thursday at 2:00 pm, a session titled, “High Speed & High Density Interconnect Using PTFE Material Flexible PCB Ribbon Cables” looks at data loss with copper cables. As ASIC bandwidth increases, data rate and number of lanes of C2M links keep increasing. When PCB cannot meet loss requirements or ASIC and IO are not on the same board, copper cables are used to connect ASIC to IO instead. The challenge is arranging multiple cables well and placing them close enough to ASIC to reduce PCB loss. The paper’s presenter suggests using a very low loss OSFP C2M flex ribbon cable that comprises a PTFE material filled with ultra-low loss filler and combined with HVLP4 is used to achieve a loss of 0.7 dB/inch at 53GHz.
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Jan 28 - Jan 30, 2025
Jan 28 - Jan 30, 2025
The must-attend event for chip, board, and systems design engineers. DesignCon is the premier high-speed communications and system design conference and exposition, offering industry-critical engineering education in the heart of electronics innovation — Silicon Valley.
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