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Cast Your Vote for the 2019 Engineer of the Year

DesignCon 2019 Engineer of the Year Award Voting Icon
Help to recognize engineering excellence by voting for the DesignCon 2019 Engineer of the Year before December 28.

The time has come to cast your vote for the DesignCon 2019 Engineer of the Year. This award is given out each year during the DesignCon event to recognize the best of the best in engineering and new product advancements at the chip, board, or system level, with a special emphasis on signal and power integrity.

Editors of Design News and the staff of DesignCon would like to offer hearty congratulations to the finalists. For this year’s award, the winner (or his/her representative) will be able to direct a $1,000 donation to any secondary educational institution in the United States. The details on each nominee are below as provided in their published biographies and by the person/s who made the nomination. Please cast your vote by following this link.

Voting closes at noon Eastern Time on Friday, December 28. The winner will be announced at DesignCon 2019, January 28-31, at the Santa Clara Convention Center, Santa Clara, CA.

The four finalists for the 2018 DesignCon Engineer of the Year Award are (click each name to see finalist’s bio and community activity):

Cast your vote for the 2019 Engineer of the Year by noon ET, December 28.

See the Official Rules of the Engineer of the Year Award.

Please click here to learn more about DesignCon and register to attend.

Al Neves

Founder & Chief Technologist, Wild River Technology

Al has 30 years of experience in the design and application development of semiconductor products, capital equipment design focused on jitter and signal integrity analysis, and has been involved with numerous successful business developments and startup activities for the last 13 years. Al is involved with the Signal Integrity community as a consultant, high-speed system-level design manager, and engineer. Recent technical accomplishments include development of platforms and methods to improve 3D electromagnetic correspondence to measure-based methods, including advancing time and frequency domain calibration methods. Al focuses on measure-based model development, package characterization, high-speed board design, low jitter design, analysis, and training. He earned a B.S. in Applied Mathematics at the University of Massachusetts.

Al has created a niche company that has shown tremendous foresight in the application of simulation techniques to design. Wild River Technology’s products, training, and practices have shed a lot of light on how to make accurate simulations.

Al has published multiple industry papers, is a member of IEEE, and a long-time, active member of the DesignCon Technical Program Committee, where he is a co-chair on Track 13.

This year at DesignCon, Al is presenting at the technical session, “S-Parameter Measurement & Fixture De-Embedding Variation Across Multiple Teams, Equipment & De-embedding Tools.”

Cast your vote for the 2019 Engineer of the Year by noon ET, December 28.

Istvan Novak

Principle SI and PI Engineer, Samtec

Istvan Novak is a Principle Signal and Power Integrity Engineer at Samtec, working on advanced signal and power integrity designs. Prior to 2018, he was a Distinguished Engineer at SUN Microsystems, later Oracle. He worked on new technology development, advanced power distribution, and signal integrity design and validation methodologies for SUN's successful workgroup server families. He introduced the industry's first 25um power-ground laminates for large rigid computer boards, and worked with component vendors to create a series of low-inductance and controlled-ESR bypass capacitors. He also served as SUN's representative on the Copper Cable and Connector Workgroup of InfiniBand, and was engaged in the methodologies, designs, and characterization of power-distribution networks from silicon to DC-DC converters. He is a Life Fellow of the IEEE with twenty-five patents to his name, author of two books on power integrity, teaches signal and power integrity courses, and maintains a popular SI/PI website.

Istvan has, in many cases, singlehandedly helped the test and measurement industry develop completely new instruments and methods of measurement. New VNA types and Scope probes and methodologies are in the market today, thanks to Istvan's efforts and openness to help others. He was responsible for the power distribution and high-speed signal integrity designs of SUN’s V880, V480, V890, V490, V440, T1000, T2000, T5120, and T5220 midrange server families. Last, but not least, Istvan has been a tremendous contributor to SI List, educating and helping engineers across the world with their SI/PI problems. Istvan is an active member of the DesignCon Technical Program Committee, sharing his expertise by participating in the review of content for multiple tracks. He is an IEEE Fellow and has been a tutor at the University of Oxford, Oxford, UK for the past 10 years. He has also been a faculty member at CEI Europe AB since 1991 and served as Vice Dean of Faculty, Associate Professor at the Technical University of Budapest.

At DesignCon 2019, Istvan will be participating in the tutorial, “How to Design Good PDN Filters,” and the technical sessions, “Effect of Power Plane Inductance on Power Delivery Networks,” “Etch Factor Impact on SI & PI,” and “How the Braid Impedance of Instrumentation Cables Impact PI & SI Measurements.”

Cast your vote for the 2019 Engineer of the Year by noon ET, December 28.

Vishram Pandit

Technology Lead (Signal/Power Integrity), Intel

Vishram Pandit has been working in the Power Integrity, Signal Integrity, and EMC field for more than 21 years—of which ~15 years were at Intel. He has been a key contributor to methodologies in on-chip power integrity, system-level power integrity impact, and signal/power integrity co-design, and successfully deploying those on various Intel products. Vishram led Power Delivery & Integrity for memory technology at Intel California from 2004 to 2008. He established SoC and DRAM device PDN solution space and chip, package, and PCB Power Integrity requirements and was Global Power Delivery Lead at the SoC Development Group from 2008 to 2011. As a part of the IP team, he worked with all global IPs spread across various geos and proliferated IP-SoC-Platform Power Integrity methodology. He is currently a Platform Architect finding ways to improve and co-optimize system power delivery spanning across PCB, Package, and Chip. He is evaluating platform PDN architecture, power rail merging, power management impact, IP/SoC PDN spec definition, decoupling strategy, and signal integrity impact on a future mobility product. Overall, during his time at Intel, Vishram led or provided technical guidance on developing various new PI/SI methodologies that helped in spec development, optimization, area savings, Platform BOM cost reduction, and product quality improvement. He had significant impact on different business units’ bottom line and certainly to the SI/PI community.

During his tenure at Intel, Vishram has received various awards for his technical contributions. He is co-author of a book, “Power Integrity for I/O Interfaces: with Signal Integrity/Power Integrity co-design,” published by Prentice-Hall in 2010, and is co-author of approximately 30 conference/ journal publications, out of which 19 publications were at DesignCon, including 3 best paper awards and 3 finalists. He received the 2018 Albert Nelson Marquis Lifetime Achievement Award for his contributions to the Signal/Power integrity field.

Vishram is an active member of the DesignCon Technical Program Committee and serves as a co-chair for Track 11, covering power integrity in power distribution networks. 

This year at DesignCon, Vishram will be presenting at the technical session, “Electrical Integrity for LPDDR5 Memory Technology.”

Cast your vote for the 2019 Engineer of the Year by noon ET, December 28.

Yuriy Shlepnev

President and Founder, Simberian

Yuriy Shlepnev is President and Founder of Simberian Inc., where he develops Simbeor electromagnetic signal integrity software. He received an M.S. degree in radio engineering from Novosibirsk State Technical University in 1983, and a Ph.D. in computational electromagnetics from Siberian State University of Telecommunications and Informatics. He was principal developer of the electromagnetic simulator for Eagleware Corporation and leading developer of electromagnetic software for simulation of signal and power distribution networks at Mentor Graphics. The results of his research are published in multiple papers and conference proceedings.

Yuriy conceived and brought to market a state of the art electromagnetic field solver tool suite and is considered an expert in his field and regularly posts teaching videos. He is a senior member of IEEE AP, MYY, EMC, and CPMT societies. He is also a Fellow of Kong’s Electromagnetics Academy and a member of the Applied Computational Electromagnetics Society (ACES).

Yuriy is active in the Technical Program Committee for DesignCon and serves as a co-chair for Track 14. At DesignCon this year, he will be speaking in the technical session, “Effect of PCB Fabrication Variations on Interconnect Loss, Delay, Impedance & Identified Material Models for 56-Gbps Interconnect Designs.”

Cast your vote for the 2019 Engineer of the Year by noon ET, December 28.

Learn more about DesignCon and register to attend.

By Engineers, For Engineers. Join our in-depth conference program with over 100 technical paper sessions, panels, and tutorials spanning 15 tracks. Learn more: DesignCon. Jan. 29-31, 2019, in Santa Clara, CA. Register to attend, hosted by Design News’ parent company UBM.
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