At the recent ODVA Industry Conference, Tom Weingartner, marketing director for the Deterministic Ethernet Technology group at Analog Devices, conducted a technical session to explore the possibilities and spur discussion on use of Ethernet technology in network edge devices. His thought-provoking proposition was to define a concept, what he calls “Low-complexity Ethernet,” that would bring reliable EtherNet/IP communication to sensors and actuators, and also identify directions that could enable brownfield installations to take advantage of bringing EtherNet/IP to edge field devices.
Of course, this approach would require an ability to reduce both the hardware cost and complexity of industrial Ethernet nodes. The presentation and accompanying paper for the ODVA Conference primarily dealt with novel approaches to reduce the hardware cost and complexity of industrial Ethernet nodes and, while not specifically addressing the reduction of software complexity, it does present an intriguing idea.
According to Weingartner, “the concept of low-complexity Ethernet holds the promise of providing cost effective, low power, reduced area connectivity for simple EtherNet/IP devices. Such a concept can be realized in an open manner coupled with advanced features in next generation Ethernet MACs and Ethernet switches.”
|Different functions and capabilities within the automation architecture increase the need for complexity and sophistication of the Ethernet solution. Source: ODVA|
By scaling a device’s communication software, it would be possible to fulfill the connectivity requirements of systems, such as EtherNet/IP, while minimizing the software footprint. The idea is that scaling, in turn, would reduce Flash and RAM hardware requirements to the point where a single chip processor with memory could be utilized in the design of a field device.
Configuration of Ethernet Nodes
Looking at the architecture of an Ethernet node, Weingartner and co-author of the paper written for the ODVA Industry Conference, David Alsup, Principal Engineer at Analog Devices, explore how it could be scaled. Their conclusion is that to reduce the cost, size, power and complexity of hardware in an EtherNet/IP edge device, the focus would be on reducing the following features:
- Target small-scale single-chip processing solution by reducing
- Processor speed/performance
- Flash memory size
- RAM size
- Reduce interconnect complexity from processor to network interface
- Reduce pin-count and complexity of network interface
They also offer an example of what constitutes a low-complexity Ethernet node, and compares a temperature transmitter that communicates today using 4-20mA technology with how these requirements would look like using Ethernet.
The conclusion is that “by taking advantage of advanced features in next generation Ethernet MACs and Ethernet Switches, it is possible to reallocate the Ethernet function from the processor into the PHY thereby creating a Low-complexity Ethernet device.”
These devices would provide the processor with a simple SPI interface to the Ethernet network. Not only does this SPI interface have the advantage that it is easier to electrically isolate from the other circuitry in the design, but it also eases the processing requirements since the controller no longer has to process every Ethernet message from the network.
“Rather than needing an A-class ARM processor to execute application and network software, a single chip processor with memory