AI's Challenges to Power and Signal Engineering Take Center Stage at DesignConAI's Challenges to Power and Signal Engineering Take Center Stage at DesignCon

It goes without saying that artificial intelligence and machine learning have become the centerpiece for many presentations and discussions at various technical conferences and shows. Informa’s DesignCon Show, taking place January 28^th through 30^th at the Santa Clara Convention Center in Santa Clara, Calif., is no exception.

We have gathered a sampling of DesignCon sessions that deal with the technical challenges of designing for and implementing AI, from the standpoint of signal integrity, power, thermal considerations, memory, and other issues. These sessions will not only hopefully give you valuable information for your engineering work but also serve as a vital forum to exchange ideas.

Panel on AI chips

On Tuesday, January 28^th, from 4:45 to 6:00 pm in Ballroom C, a panel titled, “Powering the AI Semiconductor Stack: Power Strategies for High-Performance AI Computing,” will discuss the rapid increase in power needed to drive the latest AI chips and how to address those.  The discussion will look at how high power requirements are expected to go and if the increase can be supported.  The panel will hopefully generate discussion between IC customers and power infrastructure suppliers. 

AI technologies in the data center

On Wednesday, January 29^th, from 8:00 to 8:45 am in Great America Ballroom 1, Dr. Steven Woo of Rambus will lead a presentation titled, “Technology Advancements for AI in the Data Center,” where he will give an overview of the memory, interface and security technologies critical to powering advanced computing for AI. 

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Memory and hardware Acceleration for AI workloads

Following Woo’s presentation, from 9:00 to 9:45 am in the same location will be “Accelerating AI Workloads with Composable Memory and Hardware Acceleration.” This session will present a novel approach to integrating composable memory solutions with AI and caching services. The speakers will discuss how Rambus CXL IP and hardware-accelerated compression IP can be leveraged in a fully assembled controller prototype FPGA system to achieve performance improvements for real-world workloads such as Meta Cachelib, a widely used hyperscale caching application for AI services. 

AI and signal integrity

Because signal integrity is core part of many DesignCon presentations and discussions, it is not surprising that AI’s impact on high-speed signal links is a t topic for discussion. On Wednesday from 2:00 to 2:45 pm, a panel discussion titled, “How Will AI Applications Affect High Speed Link Design?”, will delve into how power and signal integrity is affected in all aspects AI applications whether it be IC design or the power grid.

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High-speed memory for AI inference

High-speed memory is a key requirement for AI workloads, including inference models. This 3:00 pm Wednesday session titled, “GDDR Memory for High-Performance AI Inference,” will look at the role of GDDR7 memory. This presentation will discuss how Rambus and Cadence worked together to develop an integrated memory subsystem that is deployed widely in end-customer systems using TSMC advanced nodes. Also discussed will be the signal integrity challenges of implementing GDDR6 and GDDR7 at these high data rates. 

AI Power Strategies

On Thursday, January 30^th at 4:00 pm, a panel session titled, “Power Delivery Strategies for AI & Data Center ASICs: Horizontal vs. Vertical,” will explore two contrasting power delivery paradigms: horizontal (lateral) and vertical approaches. Vertical power delivery places the voltage regulator module (VRM) directly underneath the ASICs and processors on the opposite side of the PCB. VRM vendors claim to integrate necessary capacitors directly into the module package. By assembling components on the backside of the PCB, opposite the ASIC and processors, power plane losses are minimized.

Related:Upgrade Your Engineering Know-How at DesignCon

For more information on DesignCon, go here.