I am sure I have experienced parasitic osc, but never identified it in practice before. As for passing EMI I have experienced issues in passing Class B. Class A designed that I worked on require only an addition of ferrite ring on cabling inside the unit.
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On Tuesday someone asked about the Vds available for fet. Digikey has a fet selector chart that lists 4500 v for a small number of products. Is there anything to keep in mind when using these high voltages like isolation of the gate driver or keeping these voltages separate and or floating?
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One concept I have seen that prevents overlap shoot-through is to use a triangle wave to trigger the forward and reverse pair of FETs. A DC offset is increased to move more of the triangle above the trigger voltage of the Forward FETs, thus increasing the duty cycle. The triangle wave is moved downward by lowering the DC offset and moving more of the triangle into the Reverse FETs. The difference in Forward and Reverse trigger voltages is greater than the P-P voltage of the triangle wave, thus the waveform can never trigger both pairs of FETs at once. Any other schemes to share?
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From design feasibility, to development, to production, having the right information to make good decisions can ultimately keep a product from failing validation. The key is highly focused information that doesn’t come from conventional, statistics-based tests but from accelerated stress testing.
There’s a good chance that a few of the things mentioned here won't fully come to fruition in 2015 but rather much later down the line. However, as Malcolm X once said, "The future belongs to those who prepare for it today."
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