? You covered hardware interrupts, but I didn't hear about priorities. This opens a whole can of worms that get into deadlocks, semaphores, resource starvation, etc. I'm pondering the question of whether something like FreeRTOS would help in my specific case or whether it eats too many resources. Will this be discussed in this series?
jjrochow- Yep the trend really seems to be towrd high level language implementations. If can really help when you have communications ports, file systems and lots of code to write to 'pull in' a simple OS and just code in Java or C+...
Personnal experience is that almost noone uses pure asm in products anymore..C ans C+ are used mostly with a heavy emphasis on C. (emmebedded products of course) E.G. Apple uses Objective C in their IOS products: iPad, iPod, iPhone, etc.
I think the major confused of everybody it's to learn a line of compiler with startup kits to maintenance in time, because in pass to many years people wants to make to study some else more complex kits, an example, is with microchip with his 16Fxx an the next range of micro use 18F with C18 it's very diferentes! teh architecture!
Slide 13 - One thing I found with CISC was not only were there multiple cycles per instruction, but varying numbers of cycles and varying instruction lengths. An instruction could be one byte long but take 7 cycles, or might be 3 bytes long and take only 3 cycles. Very tough to pipeline. With RISC, you might want to do something really simple (check a zero bit), and then find out you still needed a 32 bit or 64 bit instruction.
?How does the CPU know that there is an interrupt and it has to save the context?
I mean, yes there is a hardware line that goes active whenever there is an interrupt, but the when does the CPU start executing it? It may not execute the ISR in the middle of the current instruction that the PC was executing. Does the CPU poll to check whether there is an active interrupt?
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