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Thanks for the archive. And thank you Jean and Jennifer.

Iron

Thank you Jean and Jennifer

Thanks Jean, interesting session today

Iron

Thanks for the interesting questions.  See you all tomorrow.  Have a great rest of your day.

Blogger

@jjrochow - you can just log back in and see the chat when you get the archived file as well as listen to the audio.

Iron

jjrochow:

Is there a log of this chat stored somewhere? I would like to review it in something other than this web browser.

Thanks.

 

You could simply cut/paste into a word document, I suppose.

Blogger

cghaba:

Does is matter if high priorities are low numbers or big numbers of the priority number range?

 

Well, I know some kernels use high numbers to represent high priority .  Frankly, I find that counter intuitive (actually being polite here) because, to me, 'Priority 1' (or 0) is more important than priority 50.  At least, that's how I view my TO DO list. :-)

Blogger

Is there a log of this chat stored somewhere? I would like to review it in something other than this web browser.

Thanks.

cghaba:

I know that in uCOS-II tasks have unique priorities. What can you do if in the application there are two tasks that should have same priority? 

 

Well, top-of-my-head, you could change the priority of one of them each time it executes.  The high priority one gets changed to a priority lower when it's done.  When the second task runs and is done, it can raise the priority back of the first task.

Blogger

Sorry..I was rebooted by our IT people and have just gotten back online.

I have a couple of questions/topics and if they have already been answered, please induldge me.

1) Do you need a clock event to schedule tasks in a RTK?

2) With tasks of equal prioity, how do you assure that all of these same-priority tasks get some CPU?

Does is matter if high priorities are low numbers or big numbers of the priority number range?

Iron

I know that in uCOS-II tasks have unique priorities. What can you do if in the application there are two tasks that should have same priority? 

Iron

aaronb:
on slides 17-19, the last slide seems to skip the last two steps on the ISR in slide 17.  This doesn't seem right- how do you get back the saved context once the higher priority task finishes running to get back to the suspended lower priority task?

What happens (in the case of uC/OS-II and uC/OS-III and I suspect possibly other kernels) is that when a task is created I setup the stack frame (slide 9) such that it looks like an interrupt JUST occurred and all the CPU registers are saved onto the task stack.  I do the same when I start an ISR (i.e. save the CPU registers in the same order) and thus, if I have to switch to a higher priority task, I don't need to go back and clean up the stack of the lower priority that thas was interrupted.  I simply resume the new task.

One thing you should note is that the stack frame on slides 8-12 are slightly incorrect, the PC and SR registers should be located at the bottom of the image and not the top.  Hopefully, some of you noticed this.

Blogger

I may do that, but usually if I can't sleep at night, I'm busy coding!

Iron

Thanks.  Have a nice day

Iron

Bob Loy:

I'm new to RT Kernels. I learn as much from these after class questions as from the class itself. Thank you Jean and everybody!

Thanks for the kind words.  That's what we want to accomplish.

BTW, If you can't sleep at night, I invite you to download the PDF of my books from the Micrium website ... get the printed (hardcover) versions. :-)

Blogger

I'm new to RT Kernels. I learn as much from these after class questions as from the class itself. Thank you Jean and everybody!

Iron

kkonesky:

For interrupt flooding, I was wondering what might be done to protect from hackers who are trying to crash your system.  If you have interrupts generated by certain IO traffic (LAN?) and you get bombarded by malicious.  What can be done at the kernel level to prevent your code from getting stuck.

 

I'm not sure, possibly your Ethernet or WiFi driver could report an unusual amount of traffic and signal a higher priority task to take corrective actions.  Maybe you would need to ignore packets for a while hoping that the hacker would stop sending you a flood of packets.

 

What would you suggest?

Blogger

@Jennifer - the post @ 2:27:13 seems to be asking the same question twice...

Iron

Lt.Dan:
I presume some tasks may not run (thread-starve?) and your real-time system doesn't behave in real-time. (i.e. things slow down).

Starvation depends on how you set your prorities and how fast your processor is.  Like I said today, if you have multiple tasks at the same priority and those take a long time to execute (and even have to be time sliced) then all task having a lower priority will starve.  I typically recommend to lower the priority of those tasks or ensure that what they have to do gets done quickly.

Blogger

For interrupt flooding, I was wondering what might be done to protect from hackers who are trying to crash your system.  If you have interrupts generated by certain IO traffic (LAN?) and you get bombarded by malicious.  What can be done at the kernel level to prevent your code from getting stuck.

Iron

mrresearch:

In case of nested interrupts, all the corresponding CPU registers will have to be saved, right? So how does it handle too deep a nesting, if that happens?

 

Well, it depends if we are talking about kernel-aware or non-kernel-aware.

For kernel-aware, the first interrupt to occur tells the kernel that this is the first interrupt.  The second to come increments that counter, and so on.  When ISR ends and 'un-nest', the counter is decremented and when the counter reaches 0, the kernel knows that it needs to go back to 'task level code'.  That's when the scheduler is invoked and the decision is made to context switch or not.

 

For non-kernel-aware ISRs, they MUST not be interrupted by kernel-aware ISRs.  Thus, non-kernel-aware ISRs must always have higher priority.

Blogger

kkonesky:

what happens in the case of an interrupt flood?  Do some get lost if there are more than the kernel can track?

 

Well, tracking of the interrupts really depends on the amount of RAM you have in the system.  uC/OS-II and uC/OS-III, for example can nest 256 levels deep.  I have never seen this situation and you would want to pray that you don't either. :-)

 

If you have more interrupts than your CPU can handle then the kernel is not your problem, it's most likely that your CPU is underpowered.

Blogger

Thank you very much Jean.

Iron

@kkonesky - I presume some tasks may not run (thread-starve?) and your real-time system doesn't behave in real-time. (i.e. things slow down).

Iron

mrresearch:

In case of nested interrupts, all the corresponding CPU registers will have to be saved, right? So how does it handle too deep a nesting, if that happens?

 

Well, it depends if we are talking about kernel-aware or non-kernel-aware.

For kernel-aware, the first interrupt to occur tells the kernel that this is the first interrupt.  The second to come increments that counter, and so on.  When ISR ends and 'un-nest', the counter is decremented and when the counter reaches 0, the kernel knows that it needs to go back to 'task level code'.  That's when the scheduler is invoked and the decision is made to context switch or not.

 

For non-kernel-aware ISRs, they MUST not be interrupted by kernel-aware ISRs.  Thus, non-kernel-aware ISRs must always have higher priority.

Blogger

what happens in the case of an interrupt flood?  Do some get lost if there are more than the kernel can track?

Iron

wayneo:

Slide 19 - Do kernel aware ISRs save the current task's registers to its own stack and the stack pointer to the TCB?  Otherwise, I can't see how the kernel can proceed directly to another task (task 2) without losing something.

 

I misread the question.  For 'kernel aware ISRs', if 'some of the registers' are saved onto a separate ISR stack then before a context switch to a new task can happen, the kernel needs to move those values pushed onto the ISR stack to the task's stack.

 

For the context switch to work, the stack frame must always have the same format.

Blogger

In case of nested interrupts, all the corresponding CPU registers will have to be saved, right? So how does it handle too deep a nesting, if that happens?

Iron

wayneo:

Slide 19 - Do kernel aware ISRs save the current task's registers to its own stack and the stack pointer to the TCB?  Otherwise, I can't see how the kernel can proceed directly to another task (task 2) without losing something.

 

That depends on the CPU.  Some CPUs automatically 'switch' to an ISR stack so those registers would be saved there.  For other CPUs, it's possible that registers are saved onto the interrupted task's stack. 

 

For non-kernel-aware ISRs it might not matter because few registers might actually need to be saved.

Blogger

Thank you, J & J ( Jennifer and Jean)

Another great lesson.

Iron

hai:

qusetion on slide 18. what's section (6) doing in ISR?

Section (6) in the ISR 'restores the CPU registers that were saved at the beginning of the ISR and executes a 'return from interrupt' instruction.

 

So, In section 5, the scheduler was called but was determined by the kernel that the interrupted task was STILL the most important task.

Blogger

Late -- have to catch up. Maybe the power will stay on today...

Iron

on slides 17-19, the last slide seems to skip the last two steps on the ISR in slide 17.  This doesn't seem right- how do you get back the saved context once the higher priority task finishes running to get back to the suspended lower priority task?

 

Iron

Slide 19 - Do kernel aware ISRs save the current task's registers to its own stack and the stack pointer to the TCB?  Otherwise, I can't see how the kernel can proceed directly to another task (task 2) without losing something.

Iron

mrresearch:

What happens to heap memory contents (if any)  when context switching?

 

Nothing actually, the context switch doesn't touch the heap at all.  The stacks for each task much be 'allocated' when tasks are created.  The stack 'could' come from the heap but that is irrelevant.

Blogger

Thank you Jean and Jennifer.

 

A question.. what happens to heap memory contents (for e.g., from malloc, if any) when context switching?

Iron

fpback:

All interrupts are non-kernel aware.

 

Interesting, so all your tasks would basically delay themselves for a certain amount of time and 'prepare' data for those ISRs?

Blogger

Thanks Jean and Jennifer.

Iron

Thanks a lot, great presentation

Iron

cghaba

Slide 18: It means that there are switches between the ISR and kernel?

 

Yes, BUT, these are JUST function calls, there are not context switches.  I just wanted to show that API functions are part of the kernel.

Blogger

qusetion on slide 18. what's section (6) doing in ISR?

Iron

Thanks Jean, and Jennifer.

Iron

@afaszholz

Use Mozilla Firefox and the complement VideoDownloadHelper and when "the balll dancing icon" appear click in it and you can download a mp3 file (before the conference ended).

Iron

Thank you Jean for a great presentation

Thank you Jennifer

Iron

Thanks Jean and Jen

Iron

Over the hump. Downhill towards Friday.

What happens to heap memory contents (if any)  when context switching?

Iron

Thanks. Good presentation.

Iron

Thanks Jennifer and Jean. Good presentation.

Iron

Thanks for another great presentation.

Iron

Kernel Aware interrupts yes/no - not sure yet.

Iron

Thanks Jean, Jennifer & Digi-Key

Iron

Thank you Sean for an informative sessions

Iron

Thanks Jean, another geart presentation.

Thanks Jennifer.

Iron

not currently using real-time kernel, could be using mix of both kernel aware and non-awarer ISR if used.

Iron

Don't know yet about non kernel aware isr's.

Iron

Usually just the failure task comes from I/O use no-aware ISR.

Iron

A few non-kernel aware interrupts would be normal.

Iron

Likley use kernel-aware ints

Iron

All interrupts are non-kernel aware.

Iron

i imagine it doesn't matter when you don't have a kernel :-)

Iron

  Jean's question was:

If you were to use a kernel, would you have 'non-kernel aware' interrupts in your application?

   Same question if you are using a kernel.  Do you have 'non-kernel aware' interrupts?

Depends on the application

Iron

zero cross detection

Iron

Depends of the project sometimes I/O is HH priority. Sometimes algorithm.

5 KHZ and 3 msec

Iron

My Corp blocks the audio.  Is there anyway to get the audio for these later as a .wma or .mpg or something?

  Thanks.

Iron

Interrupt freq is still being determined.

Iron

Slide 18: It means that there are switches between the ISR and kernel?

Iron

Got here late today - greetings from Colorado...

Iron

every 50mS and respond less than a mS

Iron

I/O task is priority in our design for processing failure task. ISR is need.

Iron

fairly low frequency UART interrupt at 1200bps

Iron

not sure; have at least one slave with an occasional 4us isr

Iron

500 uS module cycle, can only hold off other code for 50uS

 

Iron

Interrupt every 20 ms.

 

Iron

250 uS period, max ISR.

Iron

about 10 milliseconds

Iron

 Jean's question was:

What is the highest frequency interrupts in your system?  In Hertz.

   How much time do you have to react to it? 

Also for 2nd question: Priorities not yet defined.

Iron

highest priority task is typically alarm processing (vitals signs monitoring application) (computational)

Iron

highest priority task is I/O for a safety alarm responce

Iron

Higher priority is I/O task.

Iron

In our previous product, an algorithm.

Iron

I/O has higher priority for me

Iron

I/O based tasks have typically been the highest priority in my projects.

Iron

Jean's question was:

What would you say is your highest priority task?

   Is it a computation task?  An algorithm?

   Is it an I/O task? 

Third try (my posts haven't been getting through):

Priorities not yet defined.

Iron

You mean idle task have to be aware by interrupt? Or just low power status idle task?

Iron

no real-time code at this time

Iron

do you need a clock event to schedule tasks in a RTK?

with tasks of equal prioity, how do you assure that all of these same-priority tasks get some CPU?

Usually 4 to 8 and I like use ISR .

Iron

don't know at this time

Iron

uncertain of task count

Iron

Does is matter if high priorities are low numbers or big numbers of the priority number range?

Iron

Squeekin' in from Chicago...

Iron

hello from Saint Louis, MO

Iron

Today audio is better.

Iron

Hello from hot Toronto!

Iron

Hi all - The audio is live!

Hi from sunny Panama City, FL.

Iron

Hello from Arlington, Texas

 

Hello from Casper, WY

Iron

Hello from Argentina :D

Iron

Hello from Chicago

 

Iron

Hello from Longmont, CO

Iron

Hello from Dubuque, IA

 

Iron

@fbpack, I lived in Hawaii for 22 years

 

Gold

Greetings from Metro Boston. Another steamy 91 degree day!

Iron

@cghaba , todays PDF matches the one I downloaded on monday, so nothing new so far.

Hi cghaba - all the slides are the same.

@fbpack: how's it in Hawaii ? Hot and humid in the northeast here.
 

Hi Jennifer,

I have downloaded all slides last week. Will you tell us if any of them changed since then?

Iron

Greetings from Vermont

Iron

hello all from sunny (finally) Edmonton, Alberta

Iron

Florida in the house

Iron

hello from Mishawaka

Iron

Aloha from Hawai'i.

Iron

Hello, Dev from India

Iron

Hello from Albuquerque.

Iron

Hello from Beaverton, Oregon

Iron

Hello from Greensboro, NC

Iron

hello from Timisoara, Romania

Iron

cghaba:

Do you know if Rockwell PLCs use an RT kernel?

 

Yes, I believe so.

Blogger

Hey, jjrochow

Do you know if Rockwell PLCs use an RT kernel?

Iron

Good evening from Iasi, Romania

Iron

Hello from hot, but slightly less steamy, Binghamton, NY.

Iron

Hi from a hot and muggy Austin, TX

Iron

Welcome everyone! Don't forget to download today's slide deck - it's right up there next to Jean's photo!

Hello from Lexington, KY

Iron

Hello again from Rockwell Automation in sunny and very warm and humid Cleveland Ohio.

 

Good moring everybody frrom Buenos Aires.\, Argentina

Iron

G'day from Aurora ON

Iron

Good moring everybody.

Iron

Hello form Chihuahua Mexico

 

Iron

Good Afternoon From Windsor, ON

Iron

Good morning from Scottsdale, AZ

Iron

Please join our Digi-Key Continuing Education Center LinkedIn Group at http://linkd.in/yoNGeY.

See you at 2 p.m. EST!

Hello from Thessaloniki, Greece

Iron

Good morning from Portland Oregon

Iron

Good morning from GA

Iron

good morning @justheretolearn and @schap1!

Good morning from very warm NY.

Iron

Good morning from Mobile, AL

Hmmm Posts are glitchy today.  Getting slides.

Iron

For this lecture, wonder if you will touch on how to make sure you don't work at cross purposes w/the RT kernel as it does its scheduling work.  In software engineering, it's common to hear that "threads are evil" and "writing complex multithreaded applications is dangerous - avoid uncessary complexity and leave threading to the experts (i.e. either become an expert or don't do it)".  Maybe the answer is just that embedded uC apps are smaller and simpler than the apps that lead to the above admonishments, so multithread complexity is manageable, but even if that's the case I'm guessing the embedded developer probably has opportunities to shoot himself in the foot w/common scheduling design mistakes.

Thanks for the info, Jean.



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