HOME  |  NEWS  |  BLOGS  |  MESSAGES  |  FEATURES  |  VIDEOS  |  WEBINARS  |  INDUSTRIES  |  FOCUS ON FUNDAMENTALS
  |  REGISTER  |  LOGIN  |  HELP
Comments
You must login to participate in this chat. Please login.

really good ideas

thank you.

Iron

but further to learn more about the topic, very interesting sir brian...

thanks to DIGI-KEY and DESIGN NEWS for giving a lecture as part of our continuing education...

now, i am proceeding with the next topic in the archived lecture...thanks...

once again would like sir brian for giving the lecture valuable, much appreciated...definitely, i have learned from your lecture in 5 days class...

now, it's about to end the presentation. i would say FANTASTIC and GREAT JOB sir brian...thanks for having this kind of lecture a valuable...

i am now on slide 17...

i am now on slide 13 of the lecture...

i am now on slide 7 of the presentation...

i am now on slide 2...

i am now downloading the slides of this presentation as well as for future reference...

good morning once again sir brian, i am here again for the conclusion of your presentation, FUNCTIONAL VERIFICATION...

Very informative lecture

Iron

Great to have access to the recorded sessions!

Iron

Missed the live lecture

Iron

Taking the class offline

Iron

A great series of lectures this week and a lot of food for thought.

 

Iron

for anyone interested in verilog or vhdl for free...

I bought an Altera developer's kit, DE0-NANO at Digikey at a really affordable price. The development software is downloadable and has a free version to keep you busy for a very long time.

https://www.altera.com/download/sw/dnl-sw-index.jsp

enjoy.

Iron

Hello from Edmonton, Alberta.

 

Iron

Belated Thanks for a great session.

Iron

Brian - Thank you for a very interesting and informative week

Iron

Hello delayed by a couple of days due to travel

Iron

Very good presentation, lots of helpful information

Good to have the archive access

Thank you Brian and Chuck

Iron

Really appreciated all week. Thanks so much for an awesome introduction.

Iron

Speaking of lots to digest, Lunch time.

Iron

I am off to have lunch with my Girlfriend. Thanks again everyone. I have enjoyed it.

You are welcome. Hope to see you all again in the futyure.

thank you I mean...

Iron

SystemVErilog is a common language, but the different mathetical foundation for them will always exist. Easier to do certain things in certain ways. We have tried OO design and it didnt work.

I remember when RTL stood for Resistor-Transistor-Logic.  Does that mean I'm old?

Iron

Brian, thank your for the great presentations this week. I hope you come back for more.

Iron

LOL. Tomorrow I catch up with everything I havent done this week!

Is there any push to bring the RTL, Assertions, and Test Bench sections under a common language spec, or are they all too different to try to combine?

Iron

What are you presenting tomorrow?  Everyday is Friday for me.

Iron

Early stage design often uses some very simple tests to check for it breing brain dead - test reset et and possible other simple functions. During this time, constrained random testbench built. You dont want to be debugging very simple iussues with constrained random.

 

Great program throughtout the week. Thanks.

Iron

The register layer brings it all togethr in one place. A driver, for example does not have this type of informatgion. It is system specific.

Doulos is recogtnised by all of the major EDA vendors as well. Will often co-sponsor sessions at conferences.

Thank you Brian. The course gave a good overview of nowadays design verification. The course really helped to reactivate my knowledge of design verfication, while I'm currently busy at the algorithmic layer (research).

Iron

What should be the approach for verification in the early stages of design cycle?

 

Iron

It seems that through register layer virtual seq & scoreboard interacts with uvm_agent? Shouldn't this interction through port & export instead of register layar. Im unable to understand what register layar is? Is it a sort of interface?

Iron

Xilinx uses Duolo for their courses.

Iron

The register layer defines what registers exist, how data is mapped into them, possibly address map etc.

@digiotal angel - pun intended I hope!

What actually register layar is made up of?

Iron

A test can instantiate any agent that exists in your library and connect them in any way it wants, and configure them in any way they have been designed to be configured.

Thanks Brian, the class was a good intro/refresher and stimulus for further study / research ...

THe agent is part of uvm_env - yes. It is a component instantiated into the environment by the factory.

There are companies who sell UVM components for you to incorporate into large testbenches.

So it will be part of uvm_env?

Iron

The driver exists in an agent. YOu are free to write your own agents.

@tariq786

 

youtube has some simple over view and introductory videos on Systemverilog that may help start you out ...

Keep the verification seperate from the design team if you can. When they are "the same person" understand that commopn errors happen.

If we write our own classes for drivers or any other component by extending the base classes, where do they really lie in picture that you have shown in slide 10? uvm_env or uvm_test?

Iron

The more the design and verificataion team collude, the greater the possibility that they define a common error.

 

I believe that Doulos has some free classes they offer

Should the one who is writing the functional code have in mind UVM classes and methodology? Could they make easiear the job of verification team (testers and testbenchers)?

Iron

Yes - there are many poeple who offer free classes to students and engineers out of work.

 

It would be the virtual sequencer that decided to initiate a DMA. It woulod probably have been monitor the bus to know when it was free or possible. Or it could have asked the arbitrator when it could successfully do the operation. Depends if the arbitrator is in the design.

I agree verification plan is WHAT not How ... but are there elements in the plan you want to see or would demand to see that make your job doable or  easier  as it relates to transitioning into the detailed verification design where a consideration of Systemverilog / UVM is taken into account ...

For Tariq786, most EDA vendors offer schools and students extreme discounts for classes.  Just ask.

No - UVM and the earlier versions only came about in the  past 5 or 6 yyears. Magma was  more into back end and custom design and analog stuff. They diid very litttleie front end, which is where functional verification sits.

@Digital_angel

 

vendor classes are very expensive. I cant afford them as a student

Iron

You gave the example of DMA operation. Lets say we have many sequences to be performed on DUT. Which component decided the arbitration? It is the test which has to decide?

Iron

Thanks Brian.  A great week!

Iron

It takes a while to get comfortable with Object Oriented cconcepts if you come from a Verrilog background, bbut not overly difficult.

Back in the late 90's, early 2000's, did companies such as Sequence Design, Magma etc play in what is now the UVM space?

A verifciation plan needs to tell the team - what must be verified before I ship the product. Has nnothing to do with how that is to be acoompplished.

uvm course would be useful once systemverilog course is done. I mean i suggest the following pattern

systemverilog -> UVM

Iron

Vendors are having SystemVerilog Training classes and seminars (e.g. Xilinx)

 

A transaction is emphemeral. Created during simmulatioon and then dissaperars once it has been delivered.

Still thinking on what a test or verification plan needs to give to the test designer(s) that helps them transition into the actual verification design phase

 

Very thorough overview, Brian, thanks!

I was in over my head with all the abstractions of the first three days (Verilog noob), but when I saw some code examples in day four, I realized, "Hey, I could do this!"

Thanks again...

Iron

Virtual sequencers seem much like Forth programming.

Iron

How useful would a complete course on UVM be?

can uvm be used in block testing as well as system level tesing?

Iron

Why Class my_txn have no parent ? It is inherited from base class uvm_sequence_item

Iron

I guess the utility of UVM can be understand when working on big, complex  designs.

Iron

Thank you very much Brian for presenting these very demanding methodologies.

Iron

A driver connects to a single interface. So, only one driver per agent. But multiple agents and a virtual sequencer can then drive both.

Thanks Brian. You cleared up much on this evolving subject

Iron

a virtual sequencer makes requests to a sequencer. A sequencer makes requests to a driver.

Have a great weekend. Much info to digest.

Can 1 sequencer drive 2 drivers?

Iron

Not currently using UVM.

Iron

thanks Brian.  Is there going to be a follow up lecture on UVM

 

Iron

Thanks Brian - great talk, good info there! !! Would like to see more of these from you in the future!

Iron

At a higher level, which leads into the Verification Design:

What would you like to see or require in a Verification / Test Plan in a formalized (not formal verification necessarily) design environment (e.g. Verification Plan is a contract deliverable) --

Requirements flowdown/traceability from Specification to Verifcation output required -- and how do the SystemVerilog 'reports' give this traceability closure?

1/2 hours is such a short span of time...

not using UVM. It seems so abstract :(

Iron

Sorry, that I had to rush so much at the end.

Thank you. I wish we got more similar course again

Iron

What is the difference in uvm_sequencer(in agent) & virtual sequencer inside uvm_env?

Iron

Thanks Brian for the presentation.

Iron

Anyone using UVM today?

Thanks Brian, Great presentation; hope they have you back

Iron

A Great week of learning 

lots of useful info

Or there's a tab at the top as well

 

Iron

Thanks Brian for the whole course.

 

Many thanks to digikey

Iron

Thanks Brian for sharing your valuable experince with us!

Iron

@Kentj

You have to start the slideshow. It's a button in the bottom right corner.

Iron

How do you enable animations?

Iron

@MazianLab:  I really appreciate your posts.  I get called away every now and then and get lost.

Iron

******* SLIDE 13 ******

Iron

And suddenly SLIDE 12

Iron

******SLIDE 11******

Iron

******* SLIDE 11 ******

Iron

******* SLIDE 5 ******

Iron

Refresh your browser with F5

Iron

picking up day five on time 

I do not have Audio.

Iron

Lecture has not started yet?

Iron

Hello again!

@Brian:

Thank you again for your advice regarding HSL. I had time to take a look into it more deeply today and I'm convinced that I can use it for my future projects.

Iron

Hi all - Audio is live!

Hello from Albuquerque.

Iron

Cant help on medical devices. Sorry

Brian,  any input for medical device companies designing for FDA approval?

 

Agree that Formal Verification would be an interesting class

Iron

Hello from Cedar Park TX

Iron

UML was improved when they added an executable aspect to the language but many have found that going from UML to HW is difficlt. More tuned to SW.

Hello from Mich again.

Iron

So, maybe it would be good in this Continuing Education Center also to have lab classes.

Iron

any thoughts or comments on UML or Unified Modeling Language? 

http://en.wikipedia.org/wiki/Unified_Modeling_Language

Be sure to follow @designnews and @DigiKeyCEC on Twitter for the latest class information. We encourage you to Tweet about today's class using the hashtag #CEC.

Blogger

Good morning all from CA

Iron

@cghaba - to restrict talks to only tools that are available in open source format would be a little limiting. Most EDA tools are not free.

Please join our DigiKey Continuing Education Center Linkedin Group at http://linkd.in/yoNGey.

Blogger

I noticed that if you click on a persons name you can see how many posts the person has done.  There's no distinction on relevant posts.

Iron

It would be great to present a more practical course. One that will present the steps of FPGA design with a real example that could be replicated by the attendees. I don't mean all the details but including some useful tips coming from design experience.

I read more or less about OVM and UVM, but for what use if there is no tool (free or with size limitation) that I can use to exercise it. Is like learning programming without computer. 

Iron

I don't stand much on formality.

Iron

There are many directions I could have gone on with this course.

Brian, any subject you pick I'm sure will interest many people

Iron

I know some people had requested more on formal verification

And Such a broad need!  I need verification, board and mixed signal.

Iron

Yes, exactly.  All of them.  I would like to see the broad area brought into refined perspectives.

 

Couldn't think of anything on my own, but yes, FPGAs would be a good subject.

Iron

The streaming audio player will appear on this web page when the show starts at 2 p.m. ET. Note, however, that some companies block live audio streams. If you don't hear any audio when the show starts, try refreshing your browser.

Blogger

Which types of EDA tools? Front end, back end, verification, Board, mixed signal... Such a broad area.

THere is one potentially in the works for FPGAs.

Be sure to click "Today's Slide Deck" under special educational materials above right to dowload the PowerPoint for today's session.

Blogger

I would like to see how the EDA companies tools are fitting in....

 

Could you do FPGAs?

Iron

Of course, we are talking EDA related :)

I liked Denny's where you only have to be 50 to get the discount.  Some IHOPs give a 15% discount to veterans.

Iron

Thanks for the compliments. Question for all of you. If I were to do more of these in the future, what topics wuld you like me to cover?

Good evening from Iasi, Romania

Iron

Florida logging in early because y'all seem to have so much fun before the class.

Iron

Hi from sunny Florida.  I have really enjoyed your presentations so far....thanks Brian.

YEs - I have started having hotels and restaurants offer me a senior discount. Why? I still make the same impression in the bed and eat as much food! It seems strange, but I am cheap, so I use whatever discounts I can get.

I wonder if I can get my senior citizen or disabled veteran discount at Amazon.

Iron

I also see some venbdors on the Amazon site selling it for $45

 

Much better.  I'll check it out.

Iron

Hello from Ottawa, ON

Iron

Hi Oscar_eng.  I knew a Jessica Ng.  No E.

Iron

and I'll have to see if one of the book stores I get discounts from can order that book.  $70 is a bit much though until I get paid for the project I need it for.

Iron

@brian_bailey:  I let the sales rep know that TI's TINA and Linear Technologies LTSpice are much easier to use without the tutorial. :-)

Iron

The sun is shining and it is supposed to bein the high 70's tomorrow, here in Huntsville, AL.  Have a great week end.  The present ation has been very good and informative.  Thanks

Iron

Hello from San Jose!

Iron

The book is basically a set of tutorials.

 

@brian_bailey: Thanks, they are going to get back with me but you have to purchase to view there tutorials.  Since I'm evaluating it they're going to see if they can get me on.

Iron

@Kentj - take a look at this book as an alternative to the manual: http://www.eetimes.com/electronics-blogs/eda-designline-blog/4410232/Book--Analog-Design-and-Simulation-using-OrCAD-Capture-and-PSpice

 

Since I work from home every day is casual.

H Brain, everyone good morning.

Iron

Hi from San Jose

 

Iron

Everyday is casual Friday for me.

Iron

Hi from Panama City, Fl

Iron

Casual Friday is back!

Iron

Hello everyone from Chicago

Iron

I have a son-in-law that fixes IE after its release.  He tries to make it work before hand but they seem to frown on that.  Two different departments and they don't like intercommunication between departments.

Iron

Same here.  I went to Firefox.  On the occasion it doesn't work, I use Chrome.

Iron

I hate IE. It kept disconnected

Iron

I just downloaded OrCAD Lite (Complete).  How do you view the tutorial?  You seem to need to log in.  To log in you need an account.  To get an account you need a license.  There is no license with the Lite version.

Iron

GOOD MORNING, TGIF!

Iron

Not if it sounds like a sonar ping.  Those can be annoying.

Iron

Do you need me to ping you?

Good morning everyone. Are you ready for the last day?

Good Morning, everyone

Iron

Sunshining (until tomorrow (actually it will go down tonight) when we're expecting rain) and 57 F in Richmond, TX

Iron

Good morning from Edmonton, AB

Snowy again, still far away from spring.

Iron

I'm downloading a 1G byte program now and it should only take about 5 minutes.  Can you imagine downloading a 1G program at 115 baud?

Iron

One ping is reference to Hunt for Red October . I'd like to live in Montana, too.

Good morning from Portland Oregon

Iron

Pinging reminds me of the early days with a phone modem.  The phone cable went under Puget Sound and when a submarine would go by it would ping the cable with its sonar and send a lot of garbage across.  It was especially bad when downloading a large program at those slow baud rates.  It would ping near the end of an hour long download and you would have to start over.

Iron

Good morning one and all from Richmond, TX

Iron

Good Morning from GA

Iron

Good morning from Mobile, AL

Oh sure, only one ping...

Iron


Partner Zone
Latest Analysis
Take a look at the top 20 US undergraduate engineering programs. Then tell us -- did your school make the cut?
Producing high-quality end-production metal parts with additive manufacturing for applications like aerospace and medical requires very tightly controlled processes and materials. New standards and guidelines for machines and processes, materials, and printed parts are underway from bodies such as ASTM International.
Engineers at the University of San Diego’s Jacobs School of Engineering have designed biobatteries on commercial tattoo paper, with an anode and cathode screen-printed on and modified to harvest energy from lactate in a person’s sweat.
A Silicon Valley company has made the biggest splash yet in the high-performance end of the electric car market, announcing an EV that zips from 0 to 60 mph in 3.4 seconds and costs $529,000.
The biggest robot swarm to date is made of 1,000 Kilobots, which can follow simple rules to autonomously assemble into predetermined shapes. Hardware and software are open-source.
More:Blogs|News
Design News Webinar Series
7/23/2014 11:00 a.m. California / 2:00 p.m. New York
7/17/2014 11:00 a.m. California / 2:00 p.m. New York
6/25/2014 11:00 a.m. California / 2:00 p.m. New York
5/13/2014 10:00 a.m. California / 1:00 p.m. New York / 6:00 p.m. London
Quick Poll
The Continuing Education Center offers engineers an entirely new way to get the education they need to formulate next-generation solutions.
Sep 8 - 12, Get Ready for the New Internet: IPv6
SEMESTERS: 1  |  2  |  3  |  4  |  5  |  6


Focus on Fundamentals consists of 45-minute on-line classes that cover a host of technologies. You learn without leaving the comfort of your desk. All classes are taught by subject-matter experts and all are archived. So if you can't attend live, attend at your convenience.
Next Class: September 30 - October 2
Sponsored by Altera
Learn More   |   Login   |   Archived Classes
Twitter Feed
Design News Twitter Feed
Like Us on Facebook

Sponsored Content

Technology Marketplace

Copyright © 2014 UBM Canon, A UBM company, All rights reserved. Privacy Policy | Terms of Service